Synth 8-2715 syntax error near - vhdl

Question

I'm designing a basic Low Fuel Detector that turns on when the fuel is 1/3 empty or lower. My code is as follows:
ENTITY LFDetector_behav IS
PORT (Fuel3, Fuel2, Fuel1, Fuel0: IN std_logic;
FuelWarningLight: OUT std_logic);
END LFDetector_behav;
ARCHITECTURE Behavior OF LFDetector_behav IS
BEGIN
PROCESS (Fuel3, Fuel2, Fuel1, Fuel0)
BEGIN
FuelWarningLight <= [(NOT(Fuel3)) AND (NOT(Fuel2))] OR [(NOT(Fuel1)) AND (NOT(Fuel0))] AFTER 5.8 ns;
END PROCESS;
END Behavior;
I get an error near my FuelWarningLight assignment and I dont understand why, I created other designs with the exact same format that worked perfectly.
Thanks.

Answer 1

I'm not sure where your error is occuring (synth or sim), but the after keyword is not synthesisable. I'm also not sure if you have intended for this to be fully combinational or not.
Possibly try the following:
ARCHITECTURE Behavior OF LFDetector_behav IS
BEGIN
PROCESS (Fuel3, Fuel2, Fuel1, Fuel0)
BEGIN
FuelWarningLight <= ((not Fuel3) AND (not Fuel2)) OR ((not Fuel1) AND (not Fuel0));
END PROCESS;
END Behavior;
Consider using clocked processes, as below (I haven't actually synth'd this, so apologies if there are any errors).
ENTITY LFDetector_behav IS
PORT (clk, Fuel3, Fuel2, Fuel1, Fuel0: IN std_logic;
FuelWarningLight: OUT std_logic);
END LFDetector_behav;
ARCHITECTURE Behavior OF LFDetector_behav IS
BEGIN
PROCESS (clk)
BEGIN
if rising_edge(clk) then
FuelWarningLight <= ((not Fuel3) AND (not Fuel2)) OR ((not Fuel1) AND (not Fuel0));
end if;
END PROCESS;
END Behavior;