I am a student, and for my homework i was asked to create a few simple programs, a makefile, and a run script. No matter what I try, I keep receiving the same error message when typing "make" as a command in the server where I am to work on and submit this homework. I have spent many hours trying to resolve this on my own, and I believe that this error is outside the scope of my education thus far.
I have attached the makefile.
all: define calcdrawing encrypt
define: define.cpp
g++ define.cpp -o define
calcdrawing: calcdrawing.cpp
g++ calcdrawing.cpp -o calcdrawing
encrypt: encrypt.cpp
g++ encrypt.cpp -o encrypt
I receive the following error message:
Makefile:1: *** Malformed target-specific variable definition. Stop.
Any help is appreciated.
you cannot use the keyword define as you intended
replace your code make file with
all: mydefine calcdrawing encrypt
mydefine: define.cpp
g++ define.cpp -o define
calcdrawing: calcdrawing.cpp
g++ calcdrawing.cpp -o calcdrawing
encrypt: encrypt.cpp
g++ encrypt.cpp -o encrypt
change my define to any name
Related
I need to add -Werror to the already existing (Exported?) CFLAGS for a build. Right now I am just trying to extract the data CFLAGS holds. I am super new to Make and Makefiles but have to add some pre-existing build files.
Say I have a target in a makefile like this
.PHONY: add_errors
add_errors:
#flags=$(CFLAGS);\
echo $$flags;\
But the issue is, CFLAGS is a really large string that has many options set.
When the makefile is executed I get the following error
/bin/sh: 1: -marm: not found
make[2]: *** [add_errors] Error 127
Which looks like something is taking the first space as the string and then discarding the rest of it.
Inside CFLAGS, a snippet of the text is
-march=armv5te -marm -mthumb-interwork -mtune=arm926ej-s --sysroot=/opt/dspg/v2.11-rc2/sysroots/cortexa9-neon-dspg-linux-gnueabi -Wno-psabi -ggdb -I/opt/dspg/v2.11-rc2/sysroots/cortexa9-neon-dspg-linux-gnueabi/usr/include/libxml2
What can I do?
You should ask a question which actually has some relation to what you really want to do, including relevant parts of the code. This example you gave is not useful for anything so the answer we give probably won't actually help you, but:
The first advice I have for you is NEVER use the # prefix on your recipes. Or at the very least never use them until AFTER your makefile is already working 100% correctly. Suppressing make's output like that is like trying to debug while blindfolded.
The problem is not related to make at all, really: it's just shell quoting rules.
If you remove the # and look at what make prints you'll see it's running this command:
flags=-march=armv5te -marm -mthumb-interwork -mtune=arm926ej-s ...; echo $flags;
If you cut and paste that to your shell, you'll get exactly the same error.
That's because the shell command foo=bar biz baz means, set the environment variable foo to the value bar then run the command biz with the argument baz.
You need to add quoting so that the shell puts all the arguments into the flags variable:
.PHONY: add_errors
add_errors:
#flags='$(CFLAGS)';\
echo $$flags;\
will cause make to run this:
flags='-march=armv5te -marm -mthumb-interwork -mtune=arm926ej-s ...'; echo $flags;
I'm facing an issue with a simple makefile and gcc (MinGW with Windows 10).
This is my simple makefile
IJNI=-I"C:\Program Files (x86)\Java\jdk1.7.0_79\include"
IJNIWIN32=-I"C:\Program Files (x86)\Java\jdk1.7.0_79\include/win32"
CC=gcc
default: main
main: lowlevelAccess.o
$(CC) $(IJNI) $(IJNIWIN32) -c lowlevelAccess -o lowlevelAccess.o
When from a command promp I launch make, I obtain:
gcc -c -o lowlevelAccess.o lowlevelAccess.c
lowlevelAccess.c:7:17: fatal error: jni.h: No such file or directory
#include <jni.h>
^
compilation terminated.
make: *** [lowlevelAccess.o] Error 1
What is wrong?
Thank you!
You aren't adding your -I flags on the lowlevelAccess.o compilation but that's the rule that needs it (not the linking rule where you have it now).
Try adding CFLAGS += $(IJNI) $(IJNIWIN32) to your makefile (possibly use CPPFLAGS instead I'm not sure offhand which is technically more correct here).
See Variables Used by Implicit Rules for what those variables are and Catalogue of Built-In Rules (or the output from make -qp) to see what the default rules that use those variables look like.
I have the following makefile when type make i got the following output. why is gcc gets called in this case?
nasm -felf ./source/multiboot.s
gcc multiboot.o -o multiboot
gcc: error: multiboot.o: No such file or directory
gcc: fatal error: no input files
compilation terminated.
make: *** [multiboot] Error 4
makefile:
CC=gcc
ASM=nasm
ASMFLAG=-felf
SOURCE=./source/
all: multiboot
multiboot.o: $(SOURCE)multiboot.s
$(ASM) $(ASMFLAG) $(SOURCE)multiboot.s
The "all" command depends on "multiboot", but there is no explicit rule defining how to produce "multiboot". In this case, Make uses a predefined rule that understands that, if the "$target.o" target exists, then "$target" can be constructed from "$target.o" by running the linker (in this case, GCC).
It seems like the problem in this case is that your instructions for the "multiboot.o" command does not actually produce the file "multiboot.o" as output. Try simply doing:
multiboot.o: multiboot.s
(That is, without specifying the command to run). Simply declaring this dependency should, by a similar mechanism, result in an implicit rule/command to create the "multiboot.o" output from "multiboot.s".
I'm trying to do this from the command prompt:
C:/>nmake makefile
But I keep getting this error
Makefile(90) : fatal error U1000: syntax error : ')' missing in macro invocation
What does the number 90 refer to?
Any one can help?
If any one would like to see the Makefile it's here Makefile
p.s: I use windows 7
Line 90 of the Makefile is:
LDSHARED = $(CC) -shared $(if $(filter-out -g -g0,$(debugflags)),,-s)
90 is the line-number of the error. I suspect this makefile isn't meant to be used in nmake, since the syntax resembles gnu-make more than nmake.
You will probably have more luck if you run gnumake (gmake or possibly simply make).
Or, you could try to rewrite the makefile using the preprocessor macros, but it will require understanding what they are supposed to do.
http://msdn.microsoft.com/en-US/library/7y32zxwh%28v=vs.80%29.aspx
All,
I'm trying to pass variables to make from the command line. My command is below
make ARCH=arm CROSS_COMPILE=/my_dir/bin/arm-openwrt-linux-g++
The error I received is
g++: error: arm: No such file or directory
But the file 'arm-openwrt-linux-g++' does exist.
I think the problem is I need to pass varibale to sub-make files. Can some help with an example of how to pass varialbes to sub-makefile from the command-line. I have tried using the -e and export options for make, but can't seen to get anything to work.
Thanks
Content of makefile:
# GNU Make solution makefile autogenerated by Premake
# Type "make help" for usage help
ifndef config
config=debug
endif
export config
PROJECTS := json openjaus
.PHONY: all clean help $(PROJECTS)
all: $(PROJECTS)
json:
#echo "==== Building json ($(config)) ===="
#${MAKE} --no-print-directory -C .build -f json.make
openjaus: json
#echo "==== Building openjaus ($(config)) ===="
#${MAKE} --no-print-directory -C .build -f openjaus.make
So, your problem is not related to sending variables over the command line.
Your problem is that in one of the makefiles in your sub-directories, which you haven't shown us, you're using the variable $(ARCH) in an incorrect way such that the expansion of the command line is not a legal g++ command line.
Based on the error message, most likely you're adding a space somewhere where it shouldn't be, so instead of something like -fmarch=arm you're getting -fmarch= arm. Obviously this is just an example because you didn't provide nearly enough information.
One other note: we can't know how your makefiles work but typically makefiles that support a variable like CROSS_COMPILE expect it to be set to just the prefix of the cross-compilation command; in your case it would be CROSS_COMPILE=/my_dir/bin/arm-openwrt-linux-. But, your makefiles might be different.
When asking questions, it's best to if you don't immediately jump to a guess about what the answer is. First describe the problem, and that includes showing the error line as well as a few lines before it. For example in this case you're getting an error from g++ so the command line that make printed out showing you how it invoked g++ would have helped greatly.
Once you've given the underlying detail, then if you think you have an idea about what the problem is go ahead and suggest it, and/or ask about it.
If you provide the rule that invokes g++ and/or the output from make showing the g++ command line, then we can help more.
Cheers!
Here's what I think needs to happen:
You need to make sure that your sub-makefiles actually respect the $(ARCH) and $(CROSS_COMPILE) variables. Are they also generated by Premake? If so, is that how it handles cross-compilation? Check the docs.
In my test (below), I found that variables set on the command line are propagated to sub-makes, which makes me think that your sub-makefiles aren't respecting $(ARCH):
Makefile:
a:
$(MAKE) -C z
z/Makefile:
a:
#echo "MAKE=$(MAKE)"
#echo "ARCH=$(ARCH)"
Running make with no arguments:
$ make
make -C z
make[1]: Entering directory `/home/foo/test/z'
MAKE=make
ARCH=
make[1]: Leaving directory `/home/foo/test/z'
Running make ARCH=bar:
$ make ARCH=bar
make -C z
make[1]: Entering directory `/home/foo/z/z'
MAKE=make
ARCH=bar
make[1]: Leaving directory `/home/foo/z/z'