I have code sorted in nested directories like
src/cmn/abc.cpp
src/voc/xyz.cpp
And desired object output should be
obj/cmn/abc.o
obj/voc/xyz.o
The Makefile entries are
SRC_FILES := src/cmn/abc.cpp src/voc/xyz.cpp
OBJ_FILES := $(patsubst %.cpp,*.o,$(patsubst src/%,obj%,$SRC_FILES))
The generic target rule is simple (too simple) and not working as desired. It creates the obj-files right next to the src-files as it misses pattern substitution. Further it misses directory creation (like obj/voc).
.cpp.o:
#$(CC) $(CC_FLAGS) $< -o $#
How should a target be defined to achieve the desired goals from above?
Since you're using GNU make already (patsubst) you might as well use pattern rules which are much more powerful than suffix rules:
obj/%.o : src/%.c
#mkdir -p $(#D)
$(CC) $(CC_FLAGS) -c $< -o $#
Related
This is my first Makefile, and I am can't figure out some of the syntax used. The questions are marked below.
$(BUILD_DIR)/%.o: %.c $(BUILD_DIR)
$(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $#
What is the usage of "$(BUILD_DIR)" in the dependency?
What is the meaning of "$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $#" in the role?
As with most computer languages the syntax of make cannot be clear if you don't know it. If you are using GNU make the GNU make manual is your friend. In the following explanations I will assume that BUILD_DIR = build and that one of the source files is bar/foo.c.
$(BUILD_DIR) in the list of prerequisites (dependencies) tells make that the build directory (in which object files are supposed to go) must exist before the recipe is executed; logical. There must be another rule somewhere to create the directory if it does not exist yet. Something like:
$(BUILD_DIR):
mkdir -p $#
But unless you forgot to copy an important character, this dependency is terribly sub-optimal. As the last modification time of a directory changes each time its content changes (files or sub-directories added or removed), it will force the re-compilation of all source files every time the directory changes, which is not what you want. A better dependency would be order-only:
$(BUILD_DIR)/%.o: %.c | $(BUILD_DIR)
that tells make to consider only the existence of $(BUILD_DIR), not its last modification time, when deciding to re-build or not.
$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $# is just a combination of make automatic variables and functions.
$< and $# expand as the first prerequisite (bar/foo.c) and the target (build/bar/foo.o) respectively.
$(<:.c=.lst) replaces .c by .lst in $<: bar/foo.lst.
$(notdir $(<:.c=.lst)) removes the directory part: foo.lst.
All in all, for a bar/foo.c source file, and with BUILD_DIR = build, the pattern rule would be equivalent to:
build/bar/foo.o: bar/foo.c | build
$(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=build/foo.lst bar/foo.c -o build/bar/foo.o
Note that there are two different situations to consider:
All your source files are in the same directory as the Makefile (no bar/foo.c, just foo.c). Then you can simplify your recipe:
$(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(<:.c=.lst) $< -o $#
because the $(notdir...) is useless.
Your source files can be in sub-directories (bar/foo.c). Then you need the $(notdir...) in your recipe. But be warned that if you have two source files with the same base name (bar/foo.c and baz/foo.c) you will have a name conflict for $(BUILD_DIR)/foo.lst and your Makefile will not work as expected. Moreover, the order-only prerequisite of the rule should be equivalent to build/bar (or build/baz), not just build. And there should be a rule to create it if needed. If it is your case I suggest to change your pattern rule for:
$(BUILD_DIR)/%.o: %.c
mkdir -p $(dir $#)
$(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $#
There are other solutions (secondary expansion...) but there are a bit too complicated for this already too long answer.
Hello I am trying to build my C++ project. I currently have a makefile that lists out all the names of the .o files I want to make. Then I prefix the directory onto them where I want them to be compiled to. Finally, I have two basic rules that handle building each object file then the executable from those object files. For whatever reason, make is not recognizing the pattern. Here is the makefile
CXX=g++
SRC_DIR=/home/epi/jfrye_xilinx/Cosimulation/SystemC/Xilinx/lib
INC_DIR=-I/home/epi/jfrye_xilinx/Cosimulation/SystemC/Xilinx/include
INC_DIR += -I/home/epi/jfrye_xilinx/SystemC/systemc-2.3.2/include
LIB_DIR=-L/home/epi/jfrye_xilinx/SystemC/system-2.3.2/lib-linux64
LIB_TAGS=-lsystemc
OBJ_DIR=/home/epi/jfrye_xilinx/Cosimulation/Adder_PL/obj
ZYNQ_DEMO=/home/epi/jfrye_xilinx/Cosimulation/Adder_PL/bin/zynq_demo
ZYNQMP_DEMO=/home/epi/jfrye_xilinx/Cosimulation/Adder_PL/bin/zynqmp_demo
OBJS+ = memory.o trace.o debugdev.o demo-dma.o xilinx-zynq.o xilinx-zynqmp.o
OBJS += safeio.o remote-port-proto.o remote-port-sk.o remote-port-tlm.o
OBJS += remote-port-tlm-memory-master.o remote-port-tlm-memory-slave.o
OBJS += remote-port-tlm-wires.o
_ZYNQ_OBJS=zynq_demo.o
_ZYNQMP_OBJS=zynqmp_demo.o
_ZYNQ_OBJS += $(OBJS)
_ZYNQMP_OBJS += $(OBJS)
ZYNQ_OBJS=$(addprefix $(OBJ_DIR)/, $(_ZYNQ_OBJS))
ZYNPMP_OBJS=$(addprefix $(OBJDIR)/, $(_ZYNQMP_OBJS))
$(info $(ZYNQ_OBJS))
all: $(ZYNQ_DEMO) $(ZYNQMP_DEMO)
$(ZYNQ_DEMO): $(ZYNQ_OBJS)
$(ZYNQMP_DEMO): $(ZYNQMP_OBJS)
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cc
$(CXX) $(INC_DIR) $(LIB_DIR) $(LIB_TAGS) -c -o $# $<
I am getting the error:
make: *** No rule to make target
/home/epi/jfrye_xilinx/Cosimulation/Adder_PL/obj/zynq_demo.o', needed
by/home/epi/jfrye_xilinx/Cosimulation/Adder_PL/bin/zynq_demo'.
Stop.
The fourth rule should take care of zynq_demo.o correct. Why is it not recognizing a rule it can use to build that object file?
I'm not a fan of pattern rules.
When and where they apply is a little haphazard for my tastes.
A better alternative IMHO is static pattern rules.
To use these simply prefix your pattern rules with the targets that those patterns apply to.
So
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cc
$(CXX) $(INC_DIR) $(LIB_DIR) $(LIB_TAGS) -c -o $# $<
simply becomes
${ZYNC_OBJS}: $(OBJ_DIR)/%.o: $(SRC_DIR)/%.cc
$(CXX) $(INC_DIR) $(LIB_DIR) $(LIB_TAGS) -c -o $# $<
I can't tell because I don't have your source tree,
but I suspect make will now give you a different error.
Something about /home/epi/jfrye_xilinx/Cosimulation/SystemC/Xilinx/lib/zynq_demo.cc being missing maybe (???).
Hey I'm trying to build some files at the same time with different suffixes. Somehow it seems imposible to do this in one line. My makefile looks as follows:
ARCH=ar
ARCHFLAGS=r
F90=gfortran
F90FLAGS=-O2 -Wall
LDFLAGS=-llapack -lblas
SRCF=/Users/pm/bin/src
OBJF=/Users/pm/bin/objs
MODF=/Users/pm/bin/mods
LIBF=/Users/pm/bin/include
SOURCES=a.f b.f90 c.f90
OBJECTS=$(addprefix $(OBJF)/,$(addsuffix .o,$(basename $(SOURCES))))
MODULES=$(addprefix $(MODF)/,*.mod)
TARGET=lib_pm_math_lib.a
$(LIBF)/$(TARGET): $(OBJECTS)
$(ARCH) $(ARCHFLAGS) $# $(OBJECTS) $(MODULES)
obmod.clean :
rm $(OBJECTS) $(MODULES)
clean :
rm $(OBJECTS) $(MODULES) $(LIBF)/$(TARGET)
$(OBJECTS): $(OBJF)/%.o : $(addprefix $(SRCF)/,$(join %.,$(suffix $(SOURCES))))
$(F90) $(F90FLAGS) $(LDFLAGS) -c $< -o$# -J$(MODF)
#$(OBJECTS): $(OBJF)/%.o : $(subst .x, ,$(addprefix $(SRCF)/,$(addsuffix .x$(suffix $(SOURCES)),%)))
# $(F90) $(F90FLAGS) $(LDFLAGS) -c $< -o$# -J$(MODF)
#$(OBJECTS): $(OBJF)/%.o : $(SRCF)/%.f90
# $(F90) $(F90FLAGS) $(LDFLAGS) -c $< -o $# -J$(MODF)
As you can see, I already managed to define my OBJECTS. But I'm not able to creat a construct that does the same for the building part of the object. Of course my first try was to use the join without the extra dot, but this results in only the suffix, for whatever reasons. Substituting the two dots with one dot does this as well. So I'm lost. The lines that I commanded out are another interesting try, and a working version for only .f90 suffixes. Actually I was hoping for something like the following to be working:
$(OBJECTS): $(OBJF)/%.o : $(SRCF)/%.*
$(F90) $(F90FLAGS) $(LDFLAGS) -c $< -o $# -J$(MODF)
I hope it's not too messy. I posted the whole file since I bet you guy's see other problems which I didn't even think of so far. Thanks in advance!
If I'm understanding you correctly, you're wanting a suffix-based wildcard rule that you can run on multiple file suffixes. You can only have one wildcard per recipe, so there's no way to do it directly. You'll need separate rules for each suffix.
The easy solution is to copy-paste one rule and change the suffix. This can become unmanageable when you start to have a lot of suffixes. Another option is to create a rule template and use that to dynamically generate your rules for you:
# Template for build rules
# Pass a file extension for an argument
define build_rule
$(OBJF)/%.o: $(SRCF)/%.$(1)
$(F90) $(F90FLAGS) $(LDFLAGS) -c $$< -o$$# -J$(MODF)
endef
# Generate rules for each selected file extension
FILE_EXTS = f f90
$(foreach ext,$(FILE_EXTS),$(eval $(call build_rule,$(ext))))
This will dynamically generate a rule that differs only by the file extension used on the input file. To support a new file extension, simply add it to the FILE_EXTS list.
Note that when make initially parses the recipe template (inside call), it will expand variables. You have to double-up the $ in the template for anything that you don't want make to expand until the recipe is actually executed (like $# or $<).
You shouldn't need to do anything special to ensure that only the objects in the OBJECTS list are compiled. Since your default make target only lists $(OBJECTS) as a dependency, the files in $(OBJECTS) will be the only ones that get built.
In this case I'd probably just use two rules:
$(OBJF)/%.o: $(SRCF)/%.f
$(F90) $(F90FLAGS) $(LDFLAGS) -c $< -o$# -J$(MODF)
$(OBJF)/%.o: $(SRCF)/%.f90
$(F90) $(F90FLAGS) $(LDFLAGS) -c $< -o$# -J$(MODF)
You could combine them into one, but it's not really worth the effort.
I've ha makefile with following entries. Will the first rule depend on the secon rule ? So that it builds all the .o files from second files ?
all:$(PROG)
$(PROG): *.o
$(LD) -o $(PROG) -c $< $(LFLAGS)
%.o : %.c
$(CC) $(CFLAGS) -o $# -c $<
To be specific if i invoke 'make all' will it invoke the second rule if no *.o files were found ?
All other Variables have usual meaning .
No, that will not work. When you run your makefile for the first time, are there any .o files? No. So the expression *.o will expand to nothing.
Of course, your recipe for $(PROG) doesn't actually use any of the object files anyway, as written.
You can do something like this (although personally I prefer to simply list the files out by hand; it's not very common to create all new files so it's not much effort, and it's safer than just trying to grab every file in the directory):
SOURCES := $(wildcard *.c)
OBJECTS := $(SOURCES:%.c=%.o)
$(PROG): $(OBJECTS)
Our make file compiles .c source files with a static pattern rule like this:
OBJECTS = foo.o bar.o baz.o
$(OBJECTS): %.o: %.c
$(CC) $< $(C_OPTIONS) -c -o $#
I need to change one of the .c files to an Objective-C .m file. Invoking the compiler is the same for both source types, so I'd like to use the same rule and just tweak it to be more flexible. I'd rather not change the OPTIONS variable because it's also used for the linking step, etc.
Is there a way to make the rule above more flexible to accommodate both .c and .m files?
Thanks
We can add this either-or behavior to the list of things Make should be able to do easily, but isn't. Here's a way to do it, using "eval" to create a seperate rule for each object.
define RULE_template
$(1): $(wildcard $(basename $(1)).[cm])
endef
OBJECTS = foo.o bar.o baz.o
$(foreach obj,$(OBJECTS),$(eval $(call RULE_template,$(obj))))
$(OBJECTS):
$(CC) $< $(C_OPTIONS) -c -o $#
Note that this depends on the source files already existing before you run Make (foo.c or foo.m, but not both). If you're generating those sources in the same step, this won't work.
Here's a less clever, more robust method.
CPP_OBJECTS = foo.o bar.o
OBJECTIVE_OBJECTS = baz.o
OBJECTS = $(CPP_OBJECTS) $(OBJECTIVE_OBJECTS)
$(CPP_OBJECTS): %.o: %.c
$(OBJECTIVE_OBJECTS): %.o: %.m
$(OBJECTS):
$(CC) $< $(C_OPTIONS) -c -o $#
EDIT: corrected OBJECTS assignment, thanks to Jonathan Leffler.
Not really just copy to
$(OBJECTS): %.o: %.m
$(CC) $< $(C_OPTIONS) -c -o $#
The call to the same compiler is just a happy occasion. Normally you do not compile objective-c code with $(CC). That just feels strange.
But since you go in a harsh way, I won't post do-it-right solution, where you separate objective-C targets from C targets into two different $(OBJECTS)-like variables and make two rules (which you should really do). Too boring. Instead, take a hack!
OBJC_FILES:=$(subst $(wildcard *.m))
real_name = `(test -h $(1) && readlink $(1) ) || echo $(1)`
$(OBJECTS): %.o: %.c
$(GCC) $< $(C_OPTIONS) -c -o $(call real_name,$#)
$(OBJC_FILES): %.c: %.m
ln -s $< $#
And God help those who maintains it!
Btw, this obviously won't work if your m-files are generated.