Structural description of LUT5 component based on LUT4 component - vhdl

Question

Please tell me how to correctly describe the structural component of LUT5 on the basis of the LUT4 component, the problem is precisely in the correct mapping of ports.
Entity LUT5 is
Port(
A,B,C,D,E : in std_logic;
Z : out std_logic;
);
End LUT5;
Architecture Behaviour of LUT5 is
Component LUT4
Port(
A,B,C,D : in std_logic;
Z : out std_logic;
);
End Component;
Begin
??????
End
End Architecture

Answer 1

You can represent a five input lookup table by using two four input lookup tables with a selector choosing between the outputs based on the fifth bit:
library ieee;
use ieee.std_logic_1164.all;
entity lut5 is
generic (
LUTVAL: std_logic_vector (0 to 31)
);
port (
a, b, c, d, e: in std_logic;
z : out std_logic
);
end entity lut5;
architecture behaviour of lut5 is
component mux2 is
port (
a: in std_logic;
b: in std_logic;
s: in std_logic;
y: out std_logic
);
end component;
component lut4 is
generic (
LUTVAL: std_logic_vector (0 to 15)
);
port (
a, b, c, d: in std_logic;
z: out std_logic
);
end component;
signal z0, z1: std_logic;
begin
LUT4_0:
lut4
generic map (
LUTVAL => LUTVAL(0 to 15)
)
port map (
a => a,
b => b,
c => c,
d => d,
z => z0
);
LUT4_1:
lut4
generic map (
LUTVAL => LUTVAL(16 to 31)
)
port map (
a => a,
b => b,
c => c,
d => d,
z => z1
);
MUX_2_1:
mux2
port map (
a => z0,
b => z1,
s => e,
y => z
);
end architecture;
The generics are a method of delivering the lookup table contents from the top level of the design model.
Add it a small testbench:
library ieee;
use ieee.std_logic_1164.all;
entity lut5_tb is
end entity;
architecture foo of lut5_tb is
signal a, b, c, d, e: std_logic := '0';
signal z: std_logic;
constant LUTVAL: std_logic_vector (0 to 31) := x"A2201000";
signal index: natural;
begin
DUT:
entity work.lut5
generic map (
LUTVAL => LUTVAL
)
port map (
a => a,
b => b,
c => c,
d => d,
e => e,
z => z
);
STIMULI:
process
use ieee.numeric_std.all;
begin
for i in LUTVAL'RANGE loop
(e, d, c, b, a) <= to_unsigned(i,5);
index <= i;
wait for 10 ns;
end loop;
wait;
end process;
end architecture;
And we can see that it performs as a five input lookup table:
You can count the bits across the z output over time using the added index signal and find the output reconstructs the 32 bit LUTVAL (x"A2201000").
Here's the missing bits and pieces:
library ieee;
use ieee.std_logic_1164.all;
entity mux2 is
port (
a: in std_logic;
b: in std_logic;
s: in std_logic;
y: out std_logic
);
end entity;
architecture foo of mux2 is
begin
y <= a when s = '0' else
b;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity lut4 is
generic (
LUTVAL: std_logic_vector (0 to 15)
);
port (
a, b, c, d: in std_logic;
z: out std_logic
);
end entity;
architecture foo of lut4 is
constant lut: std_logic_vector := LUTVAL;
use ieee.numeric_std.all;
begin
LOOKUP:
z <= lut(to_integer(unsigned'(d,c,b,a)));
end architecture;