I am getting U in the waveform instead of proper output.I don;t understand the reason it is happening in such a way. Can anyone please correct my mistake. Providing the code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity circuit1 is port (
A, B: in std_logic;
F1 : out std_logic);
end circuit1;
architecture structural of circuit1 is
signal A_B, B_A: std_logic;--internal signal declarations for A_B and B_A
component and_1 is port (--Component declaration for and_1
i1, i2: in std_logic;
o1: out std_logic);
end component;
component nor_1 is port (--Component declaration for nor_1
i1, i2: in std_logic;
o1: out std_logic);
end component;
begin
--Component placement and connections (formally called component instantiations)
C1: and_1 port map (i1 => A, i2 => B, o1 => A_B);
C2: and_1 port map (i1 => B, i2 => A, o1 => B_A);
C3: nor_1 port map (i1 => A_B, i2 => B_A, o1 => F1);
end structural;
Here is my Test bench code. I have tried to assign different values to A and B , and want the simulation to give the output accordingly.
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity circuit1_tb is
end;
architecture bench of circuit1_tb is
component circuit1 port (
A, B: in std_logic;
F1 : out std_logic);
end component;
signal A, B: std_logic;
signal F1: std_logic;
begin
uut: circuit1 port map ( A => A,
B => B,
F1 => F1 );
stimulus: process
begin
-- Put initialisation code here
A<='1';
B<='1';
F1<='1';
-- Put test bench stimulus code here
A<='0';
B<='0';
wait for 100 ns;
A<='0';
B<='1';
wait for 100 ns;
A<='1';
B<='0';
wait for 100 ns;
A<='1';
B<='1';
wait for 100 ns;
wait;
end process;
end;
Waveform:
enter image description here
Related
this is my first time working in VHDL, and I was wondering why I am getting an error of "gt1 is not compiled in library 'xil_defaultlib', and 'gt is not declared' in struc_arch. The purpose of the code is to basically have a 2 bit comparator that will output 1 if a is greater than b.
architecture struc_arch of gt2 is
signal g1 : std_logic;
begin
gt_bit0_unit : entity work.gt0(sop_arch)
port map(
i0 => a(1),
i1 => b(0),
gt => g0
);
agtb <= gt;
end struc_arch;
And the code of the sop_arch that is referenced:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity gt2 is
port (a,b : in std_logic_vector(1 downto 0);
agtb : out std_logic);
end gt2;
architecture sop_arch of gt2 is
begin
agtb <= '1' when (a>b) else
'0';
end sop_arch;
I'm looking to implement the functions y = a and b; y = (a or b) and (c or d).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity task1_tb is
-- Port ( ); end task1_tb;
architecture Behavioral of task1_tb is
--declaring the component component task1
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC); end component;
signal y,a,b: std_logic;
signal counter: unsigned(1 downto 0):="00";
begin
uut: task1 port map(a => a, b => b, y => y );
end Behavioral;
How can I assign a (bit 1) and b (bit 2) so it will test ever possible value and make a 20ns delay between each combination? I've been trying to learn VHDL these past two days for a school project and not even sure if what I have is right.
You're looking to use a wait for <duration> in your stimulus process.
process
begin
for i in 0 to 2**2-1 loop --2**(number of input bits)-1
(a, b) <= to_unsigned(i,2);
wait for 20 ns;
end loop;
wait;
end process;
Credit to user1155120 for refinements.
Please tell me how to correctly describe the structural component of LUT5 on the basis of the LUT4 component, the problem is precisely in the correct mapping of ports.
Entity LUT5 is
Port(
A,B,C,D,E : in std_logic;
Z : out std_logic;
);
End LUT5;
Architecture Behaviour of LUT5 is
Component LUT4
Port(
A,B,C,D : in std_logic;
Z : out std_logic;
);
End Component;
Begin
??????
End
End Architecture
You can represent a five input lookup table by using two four input lookup tables with a selector choosing between the outputs based on the fifth bit:
library ieee;
use ieee.std_logic_1164.all;
entity lut5 is
generic (
LUTVAL: std_logic_vector (0 to 31)
);
port (
a, b, c, d, e: in std_logic;
z : out std_logic
);
end entity lut5;
architecture behaviour of lut5 is
component mux2 is
port (
a: in std_logic;
b: in std_logic;
s: in std_logic;
y: out std_logic
);
end component;
component lut4 is
generic (
LUTVAL: std_logic_vector (0 to 15)
);
port (
a, b, c, d: in std_logic;
z: out std_logic
);
end component;
signal z0, z1: std_logic;
begin
LUT4_0:
lut4
generic map (
LUTVAL => LUTVAL(0 to 15)
)
port map (
a => a,
b => b,
c => c,
d => d,
z => z0
);
LUT4_1:
lut4
generic map (
LUTVAL => LUTVAL(16 to 31)
)
port map (
a => a,
b => b,
c => c,
d => d,
z => z1
);
MUX_2_1:
mux2
port map (
a => z0,
b => z1,
s => e,
y => z
);
end architecture;
The generics are a method of delivering the lookup table contents from the top level of the design model.
Add it a small testbench:
library ieee;
use ieee.std_logic_1164.all;
entity lut5_tb is
end entity;
architecture foo of lut5_tb is
signal a, b, c, d, e: std_logic := '0';
signal z: std_logic;
constant LUTVAL: std_logic_vector (0 to 31) := x"A2201000";
signal index: natural;
begin
DUT:
entity work.lut5
generic map (
LUTVAL => LUTVAL
)
port map (
a => a,
b => b,
c => c,
d => d,
e => e,
z => z
);
STIMULI:
process
use ieee.numeric_std.all;
begin
for i in LUTVAL'RANGE loop
(e, d, c, b, a) <= to_unsigned(i,5);
index <= i;
wait for 10 ns;
end loop;
wait;
end process;
end architecture;
And we can see that it performs as a five input lookup table:
You can count the bits across the z output over time using the added index signal and find the output reconstructs the 32 bit LUTVAL (x"A2201000").
Here's the missing bits and pieces:
library ieee;
use ieee.std_logic_1164.all;
entity mux2 is
port (
a: in std_logic;
b: in std_logic;
s: in std_logic;
y: out std_logic
);
end entity;
architecture foo of mux2 is
begin
y <= a when s = '0' else
b;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity lut4 is
generic (
LUTVAL: std_logic_vector (0 to 15)
);
port (
a, b, c, d: in std_logic;
z: out std_logic
);
end entity;
architecture foo of lut4 is
constant lut: std_logic_vector := LUTVAL;
use ieee.numeric_std.all;
begin
LOOKUP:
z <= lut(to_integer(unsigned'(d,c,b,a)));
end architecture;
How can I make a testbench for this full adder code. I'm a newbie and would appreciate any help.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Full_Adder is
PORT(a , b , C_In : IN STD_LOGIC; S,C_Out : OUT STD_LOGIC);
end Full_Adder;
architecture Behavioral of Full_Adder is
begin
S <= a XOR b XOR C_In;
C_Out <= (a AND b) OR (a AND C_In) OR (b AND C_In);
end Behavioral;
Here's a good reference, one of the first that came up when I googled how to write a testbench.
You should google first, give it an honest shot, then come back here with more specific questions.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Full_Adder_tb is
end Full_Adder_tb;
architecture Behavioral of Full_Adder_tb is
component Full_Adder is -- component declaration
port(
a : in std_logic;
b : in std_logic;
C_in : in std_logic;
S : out std_logic;
C_out : out std_logic
);
end component;
signal a: std_logic := '0'; -- signal declarations
signal b: std_logic := '0';
signal C_in: std_logic := '0';
signal S: std_logic;
signal C_out : std_logic;
begin
uut : Full_Adder -- component instantiation
port map(
a => a, -- signal mappings
b => b,
C_in => C_in,
S => S,
C_out => C_out);
process
begin
wait 10 ns; -- wait time
a <= '0'; b <= '0'; C_in <= '1'; -- example test vector
wait 10 ns;
-- Other test vectors and waits here
end process;
end Behavioral;
I'm learning VHDL and I've come to a halt. I'd like to create a simple gate out of smaller gates (a NAND gate here). Here's the code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ANDGATE2 is
port(
x,y : in STD_LOGIC;
z : out STD_LOGIC
);
end ANDGATE2;
architecture ANDGATE2 of ANDGATE2 is
begin
z <= x AND y;
end ANDGATE2;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOTGATE1 is
port(
x : in STD_LOGIC;
z : out STD_LOGIC
);
end NOTGATE1;
architecture NOTGATE1 of NOTGATE1 is
begin
z <= NOT x;
end NOTGATE1;
library ieee;
use ieee.std_logic_1164.all;
entity NANDGATE2 is
port(
x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC
);
end NANDGATE2;
architecture NANDGATE2 of NANDGATE2 is
signal c, d: std_logic;
component NOTGATE1
port(
n_in : in STD_LOGIC;
n_out : out STD_LOGIC
);
end component;
component ANDGATE2
port(
a_in1, a_in2 : in STD_LOGIC;
a_out : out STD_LOGIC
);
end component;
begin
N0: ANDGATE2
port map(x, y, c);
N1: NOTGATE1
port map(c, d);
z <= d;
end NANDGATE2;
Here's the code from some tutorial I've been using as a template; it compiles with no problems.
library ieee;
use ieee.std_logic_1164.all;
-- definition of a full adder
entity FULLADDER is
port
(
a, b, c: in std_logic;
sum, carry: out std_logic
);
end FULLADDER;
architecture fulladder_behav of FULLADDER is
begin
sum <= (a xor b) xor c ;
carry <= (a and b) or (c and (a xor b));
end fulladder_behav;
-- 4-bit adder
library ieee;
use ieee.std_logic_1164.all;
entity FOURBITADD is
port
(
a, b: in std_logic_vector(3 downto 0);
Cin : in std_logic;
sum: out std_logic_vector (3 downto 0);
Cout, V: out std_logic
);
end FOURBITADD;
architecture fouradder_structure of FOURBITADD is
signal c: std_logic_vector (4 downto 0);
component FULLADDER
port
(
a, b, c: in std_logic;
sum, carry: out std_logic
);
end component;
begin
FA0: FULLADDER
port map (a(0), b(0), Cin, sum(0), c(1));
FA1: FULLADDER
port map (a(1), b(1), C(1), sum(1), c(2));
FA2: FULLADDER
port map (a(2), b(2), C(2), sum(2), c(3));
FA3: FULLADDER
port map (a(3), b(3), C(3), sum(3), c(4));
V <= c(3) xor c(4);
Cout <= c(4);
end fouradder_structure;
My code compiles with no errors, but with two warnings:
# Warning: ELAB1_0026: p2.vhd : (85, 0): There is no default binding for component "andgate2".(Port "a_in1" is not on the entity).
# Warning: ELAB1_0026: p2.vhd : (87, 0): There is no default binding for component "notgate1".(Port "n_in" is not on the entity).
What gives?
You need to use the same port names on your component and entity declarations.
Right now, for example in your NOTGATE1 entity declaration, you have input port x and output port z, but in the NANDGATE2 architecture, you declare the NOTGATE1 component to have ports n_in and n_out.
This won't cause problems during compilation, since compilation looks at a single unit at a time, and won't see the actual entities. In the elaboration phase, your tools will try to match up the entities to components, but this will fail since the ports don't match.
Not 100% sure, but I think the pins in your component declarations need to match up to the ones in your entity blocks:
component NOTGATE1
port(
x : in STD_LOGIC;
z : out STD_LOGIC
);
end component;
component ANDGATE2
port(
x,y : in STD_LOGIC;
z : out STD_LOGIC
);
Always use explicit port bindings in your port maps, like
port map(a_in1 => x,
a_in2 => y,
a_out => c);
It will make your code also more clear. In big projects it is the first rule of thumb.