I wanted to have every Env have its own Makefile (local, dev, production).
So I created 3 directories and a Makefile for every Directory.
Then creates a common MakeFile which includes all other child Makefiles as :
I was able to include my child commands in Parent file but the issue is
If I ran make local , it executes all commands inside Makefile.local
But instead I want each command must be ran individual
When mentioned like make local local_command or even make local_command , local_command must be executed only.
You likely want something like:
TOP_LEVEL_TARGS := dev local prod
$(TOP_LEVEL_TARGS):
make -f config/local/Makefile.$# $(filter-out $(TOP_LEVEL_TARGS), $(MAKECMDGOALS))
This will invoke a sub-make with all the command goals of the original make commands (minus the top level targets).
Related
Under FreeBSD, for some odd reason every time I execute a simple Makefile, it tries to create an obj directory under the current PWD.
I thought it might have to do with the default .OBJDIR for FreeBSD make, but setting .OBJDIR: ./ does not change this behavior.
This causes me problems down the line because it conflicts with SConstruct, but I managed to work around that by removing all read/write permissions for ./obj, however I still want to know why every time I run make, it tries to create the ./obj directory if it doesn't exist.
make does not create any ${.OBJDIR} automatically -- something in your Makefiles must be explicitly creating that (or trying to).
Could you post the makefile and/or the output of a make-run?
You can affect the value of the variable by setting MAKEOBJDIRPREFIX or MAKEOBJDIR in the environment or on command-line (neither can be set in /etc/make.conf).
See make(1) for more details.
I have a large project with multiple subdirectories. In the parent directory, I have a CMakeLists.txt file which calls functions defined in other cmake files in the same parent directory. I have a custom Makefile in one of the subdirectories that contains some target "run". When I call cmake from the parent directory, I want the "run" target located in the subdirectory makefile to execute. How should I do this ?
I understand that some people have suggested to use add_custom_target and add_custom_command, but I am still confused as to how to apply these commands to accomplish this task.
If you know, which file(s) are produced by Makefile in the subdirectory, and want to depend on these files, use add_custom_command:
add_custom_command(OUTPUT <output-file>
COMMAND make run
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/<subdir>
)
This assumes that your CMakeLists.txt have a target, which depends or uses given file.
Otherwise, if you do not care which files are produced by Makefile, use add_custom_target:
add_custom_target(<target_name> COMMAND make run
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/<subdir>
)
In both cases WORKING_DIRECTORY specifies directory which should be current for command executed.
If you want the target (in the second case) to be executed by default, add ALL option before the COMMAND.
I would like to configure my project in order to use Splint to analyse the different components.
How to add the command line into my Makefile, in a way it will ask if I want to run an analysis with Splint or just compile the program normally ?
To run splint as part of the running of make you can either add it to an existing target in the makefile or you can add a new splint/lint/etc. target that runs the command you need to run.
lint:
splint arg1 arg2
You will want to mark that target as a .PHONY so make does the right thing should a lint file ever exist.
You may also, for completeness/etc., list the files that splint operates on as prerequisites of the target. (e.g. lint: $(SOURCE_FILES) or whatever.)
there are C files in a directory and I have a makefile.
I usually use makefile to compile.
I have been wandering the role of the 'make clean'
'make clean' is just to remove files.
Though I didn't use 'make clean', t
he error and warning was shown up when there were something wrong.
I cannot realize why I need to use 'make clean' whenever I change the source file.
make is a utility is to determine automatically which pieces of a large program need to be recompiled, and issue the commands to recompile them.
To prepare to use make, you must write a file called the makefile that describes the relationships among files in your program, and the states the commands for updating each file.
Once a suitable makefile exists, each time you change some source files, this simple shell command:
make
suffices to perform all necessary recompilations. The make program uses the makefile data base and the last-modification times of the files to decide which of the files need to be updated.
We generally use make clean as a generic way to tell clean up the code.ie; remove all the compiled object files from the source code. You can name it as anything you like.
It's convention only. The convention is that clean will return you to a state where all you have is the "source" files. In other words, it gets rid of everything that can be built from something else (objects, executables, listings and so on).
So make clean ; make is expected to build everything from scratch. And, in fact, you'll often find a rule like:
rebuild: clean all
which will do both steps for you.
You should never have to do a clean unless you're wanting to (for example) copy just the source files somewhere. If you have to do so after editing a file, then your Makefile is not set up correctly.
And, if you make and get an error, you should get exactly the same error if you subsequently make without fixing said error.
GNU make automatically removes intermediate files created by implicit rules, by calling rm filename at the end. This obviously doesn't work if one of the targets was actually a directory. Take the following example:
.PHONY: all
all: test.target
%.target: tempdir.%
touch $#
tempdir.%:
mkdir -p $#
make -n reveals the action plan:
mkdir -p tempdir.test
touch test.target
rm tempdir.test
Is it possible to get GNU make to correctly dispose of intermediate directories? Perhaps by changing rm to rm -rf?
There is no way to make this happen. Although GNU make prints the command "rm", really internally it's running the unlink(2) system call directly and not invoking a shell command. There is no way to configure or modify the command that GNU make runs (except by changing the source code of course).
However, I feel I should point out that it's just not going to work to use a directory as a normal prerequisite of a target. GNU make uses time-last-modified comparison to tell when targets are up to date or not, and the time-last-modified of a directory does not follow the standard rules. The TLM of a directory is updated every time a file (or subdirectory) in that directory is created, deleted, or renamed. This means you will created the directory, then have a bunch of files that depend on it: the first one is built and has timestamp N. The last one is built and has timestamp N+x. That also sets the directory's timestamp to N+x. Then the next time you run make, it will notice that the first one has an older timestamp (N) than one of its prerequisites (the directory, at N+x), and rebuild.
And this will happen forever, until it can build the remaining "out of date" prerequisites fast enough that their timestamp is not newer than the directory.
And, if you were to drop a temporary file or editor backup file or something in that directory, it would start all over again.
Just don't do it.
Some people use an explicit shell command to create directories. Some people create them as a side-effect of the target creation. Some people use order-only prerequisites to ensure they're created on time.