How to create a pseudo-random sequence with a 16 bit LFSR - vhdl

Question

I am trying to generate a random sequence of 16 bit.
The problem is that the output is getting undefined state. I feel that this is due to parallel processing in those xor statements. So I have put in delays but it still doesn't work.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity random_data_generator is
port (
por : in STD_LOGIC;
sys_clk : in STD_LOGIC;
random_flag : in STD_LOGIC;
random_data : out STD_LOGIC_vector (15 downto 0)
);
end random_data_generator;
architecture Behavioral of random_data_generator is
signal q : std_logic_vector(15 downto 0);
signal n1,n2,n3 : std_logic;
begin
process(sys_clk)
begin
if(por='0') then
q<= "1001101001101010";
elsif(falling_edge(sys_clk)) then
if(random_flag='1') then
n1<= q(15) xor q(13);
n2<= n1 xor q(11) after 10 ns;
n3<= n2 xor q(10) after 10 ns;
q<= q(14 downto 0) & n3 after 10 ns;
end if;
end if;
end process;
random_data <= q;
end Behavioral;

Answer 1

Making some small structural changes to your LFSR:
library ieee;
use ieee.std_logic_1164.all;
entity random_data_generator is
port (
por: in std_logic;
sys_clk: in std_logic;
random_flag: in std_logic;
random_data: out std_logic_vector (15 downto 0)
);
end entity random_data_generator;
architecture behavioral of random_data_generator is
signal q: std_logic_vector(15 downto 0);
signal n1, n2, n3: std_logic;
begin
process (por, sys_clk) -- ADDED por to sensitivity list
begin
if por = '0' then
q <= "1001101001101010";
elsif falling_edge(sys_clk) then
if random_flag = '1' then
-- REMOVED intermediary products as flip flops
q <= q(14 downto 0) & n3; -- REMOVED after 10 ns;
end if;
end if;
end process;
-- MOVED intermediary products to concurrent signal assignments:
n1 <= q(15) xor q(13);
n2 <= n1 xor q(11); -- REMOVED after 10 ns;
n3 <= n2 xor q(10); -- REMOVED after 10 ns;
random_data <= q;
end architecture behavioral;
These changes remove the n1, n2, and n3 flip flops by promoting those assignments to concurrent signal assignment statements. The fundamental issue generating 'U's is that these flip flops were not initialized. They were flip flops because their assignment was inside the if statement with an elsif condition on the falling edge of sys_clk.
Adding a testbench:
library ieee;
use ieee.std_logic_1164.all;
entity rng_tb is
end entity;
architecture foo of rng_tb is
signal por: std_logic;
signal sys_clk: std_logic := '0';
signal random_flag: std_logic;
signal random_data: std_logic_vector (15 downto 0);
begin
DUT:
entity work.random_data_generator
port map (
por => por,
sys_clk => sys_clk,
random_flag => random_flag,
random_data => random_data
);
CLOCK:
process
begin
wait for 5 ns;
sys_clk <= not sys_clk;
if now > 2800 ns then
wait;
end if;
end process;
STIMULI:
process
begin
por <= '1';
random_flag <= '0';
wait until falling_edge(sys_clk);
por <= '0';
wait until falling_edge(sys_clk);
wait for 1 ns;
por <= '1';
wait until falling_edge(sys_clk);
random_flag <= '1';
wait;
end process;
end architecture;
Analyzing both, elaborating and simulating the testbench gives:
Showing a pseudo-random sequence with a length longer than 16 using a 16 bit Linear Feedback Shift Register (LFSR).