I'm trying to sum the sample values of 8 ADC's. Divide them by 8 and return the result via a DAC. I've made a case statement that provides the user to choose between summing the whole or just outputting one channel.
The problem that I encounter is that the result is "flickering". It often does what it must do, but sometimes it gives what it seems higher values.
Also the individual channels seem much much worse than the summed value. I got the feeling it synthesizes two different things for summing and individual channels or something.
I think it might have something do with how I sum the vectors, but I'm not experienced enough to tell if what I'm doing is wrong or not.
Does anybody perhaps know what I'm doing wrong.
The code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sum IS
PORT(
CLK_IN : IN STD_LOGIC; -- 200MHz
RESET : IN STD_LOGIC;
SUM_EN : IN STD_LOGIC;
SUM_VALID : IN STD_LOGIC;
CHANNEL_IN_1 : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
CHANNEL_IN_2 : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
CHANNEL_IN_3 : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
CHANNEL_IN_4 : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
CHANNEL_IN_5 : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
CHANNEL_IN_6 : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
CHANNEL_IN_7 : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
CHANNEL_IN_8 : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
MODE_DATA : IN std_logic_vector(3 DOWNTO 0);
DATA_OUT : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := x"80";
SUM_READY : OUT STD_LOGIC := '0');
END sum;
ARCHITECTURE behaviour OF sum IS
-- input output registers
SIGNAL r_sum_en : STD_LOGIC := '0';
SIGNAL r_sum_en_edge : STD_LOGIC := '0';
SIGNAL r_sum_valid : STD_LOGIC := '0';
SIGNAL r_sum_ready : STD_LOGIC := '0';
SIGNAL r_channel_in_1 : STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
SIGNAL r_channel_in_2 : STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
SIGNAL r_channel_in_3 : STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
SIGNAL r_channel_in_4 : STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
SIGNAL r_channel_in_5 : STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
SIGNAL r_channel_in_6 : STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
SIGNAL r_channel_in_7 : STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
SIGNAL r_channel_in_8 : STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := (others => '0');
SIGNAL r_mode_data : STD_LOGIC_VECTOR( 3 DOWNTO 0 ) := (others => '0');
SIGNAL r_data_out : STD_LOGIC_VECTOR( 7 DOWNTO 0 ) := x"80";
-- logic signals
TYPE machine IS (idle, initialise, summing, waiting, averaging, delivering);
SIGNAL state : machine;
BEGIN
r_channel_in_1 <= CHANNEL_IN_1 WHEN r_sum_en = '1' ELSE x"80";
r_channel_in_2 <= CHANNEL_IN_2 WHEN r_sum_en = '1' ELSE x"80";
r_channel_in_3 <= CHANNEL_IN_3 WHEN r_sum_en = '1' ELSE x"80";
r_channel_in_4 <= CHANNEL_IN_4 WHEN r_sum_en = '1' ELSE x"80";
r_channel_in_5 <= CHANNEL_IN_5 WHEN r_sum_en = '1' ELSE x"80";
r_channel_in_6 <= CHANNEL_IN_6 WHEN r_sum_en = '1' ELSE x"80";
r_channel_in_7 <= CHANNEL_IN_7 WHEN r_sum_en = '1' ELSE x"80";
r_channel_in_8 <= CHANNEL_IN_8 WHEN r_sum_en = '1' ELSE x"80";
r_sum_en <= SUM_EN;
r_mode_data <= MODE_DATA;
r_sum_valid <= SUM_VALID;
DATA_OUT <= r_data_out;
SUM_READY <= r_sum_ready;
PROCESS (CLK_IN, RESET) IS
VARIABLE average : STD_LOGIC_VECTOR(11 DOWNTO 0) := (others => '0');
VARIABLE hold_channel_1 : STD_LOGIC_VECTOR(11 DOWNTO 0) := (others => '0');
VARIABLE hold_channel_2 : STD_LOGIC_VECTOR(11 DOWNTO 0) := (others => '0');
VARIABLE hold_channel_3 : STD_LOGIC_VECTOR(11 DOWNTO 0) := (others => '0');
VARIABLE hold_channel_4 : STD_LOGIC_VECTOR(11 DOWNTO 0) := (others => '0');
VARIABLE hold_channel_5 : STD_LOGIC_VECTOR(11 DOWNTO 0) := (others => '0');
VARIABLE hold_channel_6 : STD_LOGIC_VECTOR(11 DOWNTO 0) := (others => '0');
VARIABLE hold_channel_7 : STD_LOGIC_VECTOR(11 DOWNTO 0) := (others => '0');
VARIABLE hold_channel_8 : STD_LOGIC_VECTOR(11 DOWNTO 0) := (others => '0');
BEGIN
IF RESET = '1' THEN
r_sum_ready <= '0';
r_data_out <= x"80";
hold_channel_1 := (others => '0');
hold_channel_2 := (others => '0');
hold_channel_3 := (others => '0');
hold_channel_4 := (others => '0');
hold_channel_5 := (others => '0');
hold_channel_6 := (others => '0');
hold_channel_7 := (others => '0');
hold_channel_8 := (others => '0');
ELSIF rising_edge(CLK_IN) THEN
CASE state IS
WHEN idle =>
r_sum_en_edge <= r_sum_en;
IF r_sum_en = '1' AND r_sum_en_edge = '0' THEN
state <= initialise;
ELSE state <= idle; END IF;
r_sum_ready <= '0';
r_sum_ready <= '0';
r_data_out <= x"80";
hold_channel_1 := x"080";
hold_channel_2 := x"080";
hold_channel_3 := x"080";
hold_channel_4 := x"080";
hold_channel_5 := x"080";
hold_channel_6 := x"080";
hold_channel_7 := x"080";
hold_channel_8 := x"080";
WHEN initialise =>
IF r_sum_valid = '1' THEN
state <= summing;
hold_channel_1(7 DOWNTO 0) := r_channel_in_1;
hold_channel_2(7 DOWNTO 0) := r_channel_in_2;
hold_channel_3(7 DOWNTO 0) := r_channel_in_3;
hold_channel_4(7 DOWNTO 0) := r_channel_in_4;
hold_channel_5(7 DOWNTO 0) := r_channel_in_5;
hold_channel_6(7 DOWNTO 0) := r_channel_in_6;
hold_channel_7(7 DOWNTO 0) := r_channel_in_7;
hold_channel_8(7 DOWNTO 0) := r_channel_in_8;
ELSE
state <= initialise;
END IF;
r_sum_ready <= '0';
WHEN summing =>
CASE r_mode_data IS
WHEN x"0" => average := hold_channel_1 + hold_channel_2 + hold_channel_3 + hold_channel_4 + hold_channel_5 + hold_channel_6 + hold_channel_7 + hold_channel_8 ;
WHEN x"1" => average := hold_channel_1;
WHEN x"2" => average := hold_channel_2;
WHEN x"3" => average := hold_channel_3;
WHEN x"4" => average := hold_channel_4;
WHEN x"5" => average := hold_channel_5;
WHEN x"6" => average := hold_channel_6;
WHEN x"7" => average := hold_channel_7;
WHEN x"8" => average := hold_channel_8;
WHEN others => null;
END CASE;
state <= waiting;
r_sum_ready <= '0';
WHEN waiting =>
state <= averaging;
r_sum_ready <= '0';
WHEN averaging =>
CASE r_mode_data IS
WHEN x"0" => r_data_out <= average (10 DOWNTO 3);
WHEN others => r_data_out <= average (7 DOWNTO 0);
END CASE;
r_sum_ready <= '0';
state <= delivering;
WHEN delivering =>
r_sum_ready <= '1';
IF r_sum_en = '1' THEN
state <= initialise;
ELSE state <= idle; END IF;
WHEN others =>
state <= idle;
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE;
Related
I am not very good at programming vhdl and I am running up to this error:
Error (10818): Can't infer register for "Current_Number_32[0]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[1]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[2]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[3]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[4]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[5]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[6]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[7]" at Receiver.vhd(123) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[8]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[9]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[10]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[11]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[12]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[13]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[14]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[15]" at Receiver.vhd(106) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[16]" at Receiver.vhd(89) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[17]" at Receiver.vhd(89) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "Current_Number_32[18]" at Receiver.vhd(89) because it does not hold its value outside the clock edge
code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Receiver is
Port ( SYS_CLK : in STD_LOGIC;
RST : in STD_LOGIC;
DATA_ACK : out STD_LOGIC;
DATA_VALID : in STD_LOGIC;
DATA_BUS_8 : in STD_LOGIC_VECTOR (7 downto 0);
DIGIT_1 : out STD_LOGIC_VECTOR (6 downto 0);
DIGIT_2 : out STD_LOGIC_VECTOR (6 downto 0);
DIGIT_3 : out STD_LOGIC_VECTOR (6 downto 0);
DIGIT_4 : out STD_LOGIC_VECTOR (6 downto 0);
DIGIT_5 : out STD_LOGIC_VECTOR (6 downto 0);
DIGIT_6 : out STD_LOGIC_VECTOR (6 downto 0);
DIGIT_7 : out STD_LOGIC_VECTOR (6 downto 0);
DIGIT_8 : out STD_LOGIC_VECTOR (6 downto 0));
end Receiver;
architecture Behavioral of Receiver is
signal Current_Number_32 : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
function BitsToDisplay (Bits : STD_LOGIC_VECTOR (3 downto 0) := (others => '0')) return STD_LOGIC_VECTOR is
variable DisplayBits : STD_LOGIC_VECTOR (6 downto 0);
begin
case Bits is
when "0000" => DisplayBits := "1111110";
when "0001" => DisplayBits := "0110000";
when "0010" => DisplayBits := "1101110";
when "0011" => DisplayBits := "1111001";
when "0100" => DisplayBits := "0110011";
when "0101" => DisplayBits := "1011011";
when "0110" => DisplayBits := "1011111";
when "0111" => DisplayBits := "1110000";
when "1000" => DisplayBits := "1111111";
when "1001" => DisplayBits := "1111101";
when "1010" => DisplayBits := "1110111";
when "1011" => DisplayBits := "0011111";
when "1100" => DisplayBits := "1001111";
when "1101" => DisplayBits := "0111101";
when "1110" => DisplayBits := "1001111";
when "1111" => DisplayBits := "1000111";
when others => DisplayBits := "0000001";
end case;
return DisplayBits;
end function;
begin
Communication : process (SYS_CLK,RST,DATA_ACK,DATA_VALID,DATA_BUS_8)
variable Section_1 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
variable Section_2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
variable Section_3 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
variable Section_4 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
variable Current_Section : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
variable Stage : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
begin
if (RST = '1') then
DATA_ACK <= '0';
Current_Number_32 <= (others => '0');
Section_1 := (others => '0');
Section_2 := (others => '0');
Section_3 := (others => '0');
Section_4 := (others => '0');
Current_Section := (others => '0');
Stage := (others => '0');
elsif rising_edge(SYS_CLK) then
if (Current_Section = "00") then
if (Stage = "00") and rising_edge(DATA_VALID) then
Section_1 := DATA_BUS_8;
Stage := "01";
end if;
if (Stage = "01") and (DATA_ACK = '1') then
DATA_ACK <= '0';
Stage := "00";
Current_Section := "01";
end if;
if (Stage = "01") and falling_edge(DATA_VALID) then
DATA_ACK <= '1';
end if;
end if;
if (Current_Section = "01") then
if (Stage = "00") and rising_edge(DATA_VALID) then
Section_2 := DATA_BUS_8;
Stage := "01";
end if;
if (Stage = "01") and (DATA_ACK = '1') then
DATA_ACK <= '0';
Stage := "00";
Current_Section := "10";
end if;
if (Stage = "01") and falling_edge(DATA_VALID) then
DATA_ACK <= '1';
end if;
end if;
if (Current_Section = "10") then
if (Stage = "00") and rising_edge(DATA_VALID) then
Section_3 := DATA_BUS_8;
Stage := "01";
end if;
if (Stage = "01") and (DATA_ACK = '1') then
DATA_ACK <= '0';
Stage := "00";
Current_Section := "11";
end if;
if (Stage = "01") and falling_edge(DATA_VALID) then
DATA_ACK <= '1';
end if;
end if;
if (Current_Section = "11") then
if (Stage = "00") and rising_edge(DATA_VALID) then
Section_4 := DATA_BUS_8;
Stage := "01";
end if;
if (Stage = "01") and (DATA_ACK = '1') then
Current_Number_32(31 downto 24) <= Section_1;
Current_Number_32(23 downto 16) <= Section_2;
Current_Number_32(15 downto 8) <= Section_3;
Current_Number_32(7 downto 0) <= Section_4;
DATA_ACK <= '0';
Stage := "00";
Current_Section := "00";
end if;
if (Stage = "01") and falling_edge(DATA_VALID) then
DATA_ACK <= '1';
end if;
end if;
end if;
end process Communication;
Display : process (SYS_CLK,RST,DIGIT_1,DIGIT_2,DIGIT_3,DIGIT_4,DIGIT_5,DIGIT_6,DIGIT_7,DIGIT_8)
begin
if (RST = '1') then
DIGIT_8 <= (others => '0');
DIGIT_7 <= (others => '0');
DIGIT_6 <= (others => '0');
DIGIT_5 <= (others => '0');
DIGIT_4 <= (others => '0');
DIGIT_3 <= (others => '0');
DIGIT_2 <= (others => '0');
DIGIT_1 <= (others => '0');
else
DIGIT_8 <= BitsToDisplay(Current_Number_32(3 downto 0));
DIGIT_7 <= BitsToDisplay(Current_Number_32(7 downto 4));
DIGIT_6 <= BitsToDisplay(Current_Number_32(11 downto 8));
DIGIT_5 <= BitsToDisplay(Current_Number_32(15 downto 12));
DIGIT_4 <= BitsToDisplay(Current_Number_32(19 downto 16));
DIGIT_3 <= BitsToDisplay(Current_Number_32(23 downto 20));
DIGIT_2 <= BitsToDisplay(Current_Number_32(27 downto 24));
DIGIT_1 <= BitsToDisplay(Current_Number_32(31 downto 28));
end if;
end process Display;
end Behavioral;
Can anyone please explain what I am doing wrong here?
I have added this code as a block to a block diagram with two other codes but before I did that compiling revealed no errors.
This code does not need to run on an actual fpga because this is a school assignment so I only need to simulate it. does that remove this error?
Trim your sensitivity list down to this:
process (SYS_CLK,RST)
You don't want to execute the process when input data changes. Only when the clock or reset changes.
I have to develop a SDRAM controller for a class project in VHDL. But this is my first time working with VHDL, that has a very important learning curve.
I have downloaded a SDRAM controller from github (https://github.com/christianmiyoshi/SDRAM_Controller_VHDL/blob/master/sdram_controller.vhd) and I am trying to complete it.
I am trying to write a data in an address and later read it, but I cant read a single data. I dont know if my problem is in the writing or in the reading process.
Can anybody help me, please?
Thank you all!
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_controller is
port(
clk : in std_logic;
reset: in std_logic;
refresh: in std_logic;
read_write_enable: in std_logic;
write_n: in std_logic;
address: in std_logic_vector(21 downto 0);
data_in: in std_logic_vector(15 downto 0);
dqmu: in std_logic;
dqml: in std_logic;
ready: out std_logic;
done: out std_logic;
data_out: out std_logic_vector(15 downto 0);
single_burst: in std_logic; --0 single y 1 burst
SDRAM_CKE: out std_logic;
SDRAM_CS_N: out std_logic;
SDRAM_RAS_N: out std_logic;
SDRAM_CAS_N: out std_logic;
SDRAM_WE_N: out std_logic;
SDRAM_BA: out std_logic_vector(1 downto 0);
SDRAM_SA: out std_logic_vector(11 downto 0);
SDRAM_DQ: inout std_logic_vector(15 downto 0);
SDRAM_DQM: out std_logic_vector(1 downto 0)
);
end entity;
architecture behavior of ram_controller is
type state_type is (init_ckeLow, init_stableClock, init_wait, init_nopCommand, init_prechargeAll, init_refresh_1, init_mode, init_refresh_2, idle, refresh_state, activate_row, activate_rcd, read_write, ras1, ras2, precharge);
signal state: state_type := init_ckeLow;
signal ticks: std_logic_vector(7 downto 0) := (others => '0');
signal ticks_ref: integer := 0;
signal ticks_ref_refresh: integer := 0;
constant burstMode: std_logic := '0';
constant casLatency: std_logic_vector(2 downto 0) := "010";
constant burstType: std_logic := '0';
constant burstLength: std_logic_vector(2 downto 0) := "000";
--signal highz_output: std_logic:= '0';
constant MODE_REG: std_logic_vector(11 downto 0) := "00" & burstMode & "00" & casLatency & burstType & burstLength;
constant MODE_REG_BURST: std_logic_vector(11 downto 0) := "000000100111";
signal command: std_logic_vector(3 downto 0);
signal row: std_logic_vector(11 downto 0);
signal column: std_logic_vector(7 downto 0);
signal bank: std_logic_vector(1 downto 0);
signal sd_busdir_x: std_logic:='0';
-- Command truth table
-- CS_N, RAS_N, CAS_N, WE_N
constant CMD_ACTIVATE: std_logic_vector(3 downto 0) := "0011";
constant CMD_PRECHARGE: std_logic_vector(3 downto 0) := "0010";
constant CMD_WRITE: std_logic_vector(3 downto 0) := "0100";
constant CMD_READ: std_logic_vector(3 downto 0) := "0101";
constant CMD_MODE: std_logic_vector(3 downto 0) := "0000";
constant CMD_NOP: std_logic_vector(3 downto 0) := "0111";
constant CMD_REFRESH: std_logic_vector(3 downto 0) := "0001";
signal address_buffer: std_logic_vector(21 downto 0) := (others => '0');
signal data_in_buffer: std_logic_vector(15 downto 0) := (others => '0');
signal dqu_buffer: std_logic := '0';
signal dql_buffer: std_logic := '0';
signal ready_buffer: std_logic := '0';
signal done_buffer: std_logic := '0';
signal data_out_buffer: std_logic_vector(15 downto 0) := (others => '0');
signal CKE: std_logic;
signal CS_N: std_logic;
signal RAS_N: std_logic;
signal CAS_N: std_logic;
signal WE_N: std_logic;
signal BA: std_logic_vector(1 downto 0);
signal SA: std_logic_vector(11 downto 0);
signal DQ: std_logic_vector(15 downto 0);
signal DQM: std_logic_vector(1 downto 0);
signal contador : std_logic_vector(15 downto 0) := x"0000";
signal modo: std_logic := '0';
begin
(CS_N, RAS_N, CAS_N, WE_N) <= command;
SDRAM_CKE <= CKE;
SDRAM_CS_N <= CS_N;
SDRAM_RAS_N <= RAS_N;
SDRAM_CAS_N <= CAS_N;
SDRAM_WE_N <= WE_N;
SDRAM_BA <= BA;
SDRAM_SA <= SA;
--SDRAM_DQ <= DQ;
SDRAM_DQM <= DQM;
--SA <= address_buffer;
SDRAM_DQ <= data_in_buffer when sd_busdir_x = '1' else (others => 'Z');
DQM <= dqu_buffer & dql_buffer;
ready <= ready_buffer;
done <= done_buffer;
data_out <= data_out_buffer;
bank <= address(21 downto 20);
row <= address(19 downto 8);
column <= address(7 downto 0);
process(clk, reset)
begin
if reset = '0' then
state <= init_ckeLow;
ticks_ref <= 0;
elsif rising_edge(clk) then
if ticks_ref /= 0 then
ticks_ref <= ticks_ref - 1;
else
-- Micron datasheet instructions
-- Frequency = 100 Mhz => period of 10ns
-- 1: Apply Vdd and Vddq simultaneously
case state is
when init_ckeLow =>
-- 2: Assert and hold CKE ant LVTTL logic low
ticks_ref <= 10;
CKE <= '0';
state <= init_stableClock;
when init_stableClock =>
-- 3: Provide stable clock
ticks_ref <= 10;
state <= init_wait;
when init_wait=>
-- 4: Wait at least 100us
-- 5: bring cke high at some point of the period
-- with command inhibit or nop
--ticks_ref <= 10000;
ticks_ref <= 2; -- debugadd
state <= init_nopCommand;
when init_nopCommand =>
--ticks_ref <= 10000;
ticks_ref <= 2; -- debug
CKE <= '1';
command <= CMD_NOP;
state <= init_prechargeAll;
when init_prechargeAll =>
-- 6: perform precharge all
-- 7: wait at leas t_RP
command <= CMD_PRECHARGE;
BA <= "00";
SA(10) <= '1'; -- all banks
ticks_ref <= 2;
ticks_ref_refresh <= 8;
state <= init_refresh_1;
when init_refresh_1 =>
-- auto refresj period: < 64 ns
if ticks_ref_refresh = 0 then
state <= init_mode;
else
ticks_ref_refresh <= ticks_ref_refresh - 1;
command <= CMD_REFRESH;
ticks_ref <= 7;
end if;
when init_mode =>
command <= CMD_MODE;
if single_burst = '0' then
SA <= MODE_REG;
modo <= '0';
else
SA <= MODE_REG_BURST;
modo <= '1';
end if;
BA <= "00";
ticks_ref <= 2;
ticks_ref_refresh <= 8;
state <= init_refresh_2;
when init_refresh_2 =>
if ticks_ref_refresh = 0 then
state <= idle;
--done_buffer <= '1';
else
ticks_ref_refresh <= ticks_ref_refresh - 1;
command <= CMD_REFRESH;
ticks_ref <= 7;
end if;
when idle =>
done_buffer <= '0';
contador <= (others => '0');
if read_write_enable = '1' then
-- tras: active to precharge: 45 ns min, 120000ns max
state <= activate_row;
command <= CMD_ACTIVATE;
SA <= row;
BA <= bank;
--done_buffer <= '0';
elsif refresh = '1' then
state <= refresh_state;
command <= CMD_REFRESH;
ticks_ref <= 7;
--done_buffer <= '0';
end if;
when refresh_state =>
state <= idle;
--done_buffer <= '1';
when activate_row =>
--trcd 20 ns
command <= CMD_NOP;
state <= activate_rcd;
data_in_buffer <= data_in;
ticks_ref <= 1;
when activate_rcd =>
-- trcs = 20ns min
state <=read_write;
SA <= "0000" & column;
if write_n = '0' then
command <= CMD_WRITE;
dqu_buffer <= dqmu;
dql_buffer <= dqml;
sd_busdir_x <= '1';
else
command <= CMD_READ;
end if;
when read_write =>
--command <= CMD_NOP;
state <= ras1;
--if modo='0' then
--sd_busdir_x <= '0';
--end if;
when ras1 =>
state <= ras2;
command <= CMD_NOP;
when ras2 =>
-- trp = 20ns min
if modo='1' and contador <= x"00FF" then
data_in_buffer <= data_in;
state <= ras2;
contador <= contador +1;
else
contador <= (others => '0');
state <= precharge;
sd_busdir_x <= '0';
command <= CMD_PRECHARGE;
SA(10) <= '1';
data_out_buffer <= SDRAM_DQ;
ticks_ref <= 2;
end if;
when precharge =>
state <= idle;
done_buffer <= '1';
ticks_ref <= 1;
end case;
end if;
end if;
end process;
end architecture;
[enter image description here][1]
[1]: https://i.stack.imgur.com/CaqqL.png
I am currently working on a game using VHDL as a programming language. I have been able to avoid laches from the start but on this one, I am completely lost...
I try to increment the level number when my small Mario reaches the end platform (to switch to the next level). So when he reaches this platform the signal nextLevel_i worth '1'.
I have implemented the code as follow:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity level is
port (
clk_i : in std_Logic;
reset_i : in std_Logic;
nextLevel_i : in std_Logic;
elem01_o : out std_logic_vector (13 downto 0);
elem02_o : out std_logic_vector (13 downto 0);
elem03_o : out std_logic_vector (13 downto 0);
elem04_o : out std_logic_vector (13 downto 0);
elem05_o : out std_logic_vector (13 downto 0);
elem06_o : out std_logic_vector (13 downto 0);
elem07_o : out std_logic_vector (13 downto 0);
elem08_o : out std_logic_vector (13 downto 0);
elem09_o : out std_logic_vector (13 downto 0);
elem10_o : out std_logic_vector (13 downto 0);
elem11_o : out std_logic_vector (13 downto 0);
elem12_o : out std_logic_vector (13 downto 0);
elem13_o : out std_logic_vector (13 downto 0);
elem14_o : out std_logic_vector (13 downto 0);
elem15_o : out std_logic_vector (13 downto 0);
elem16_o : out std_logic_vector (13 downto 0);
elem17_o : out std_logic_vector (13 downto 0);
elem18_o : out std_logic_vector (13 downto 0);
elem19_o : out std_logic_vector (13 downto 0);
elem20_o : out std_logic_vector (13 downto 0)
);
end level;
architecture Behavioral of level is
signal currentLevel_s : integer range 0 to 127 := 0;
begin
processLevel : process (currentLevel_s)
begin
elem01_o <= (others => '0');
elem02_o <= (others => '0');
elem03_o <= (others => '0');
elem04_o <= (others => '0');
elem05_o <= (others => '0');
elem06_o <= (others => '0');
elem07_o <= (others => '0');
elem08_o <= (others => '0');
elem09_o <= (others => '0');
elem10_o <= (others => '0');
elem11_o <= (others => '0');
elem12_o <= (others => '0');
elem13_o <= (others => '0');
elem14_o <= (others => '0');
elem15_o <= (others => '0');
elem16_o <= (others => '0');
elem17_o <= (others => '0');
elem18_o <= (others => '0');
elem19_o <= (others => '0');
elem20_o <= (others => '0');
case currentLevel_s is
when 1 =>
elem01_o <= "11111001010000";
elem02_o <= "01110000110000";
elem03_o <= "01110001010000";
elem04_o <= "01110001110000";
elem05_o <= "01110010010000";
elem06_o <= "01110010110000";
elem07_o <= "01110011010000";
elem08_o <= "01110011110000";
elem09_o <= "01110100010000";
elem10_o <= "01110100110000";
elem11_o <= "01110101010000";
elem12_o <= "01110101110000";
elem13_o <= "01110110010000";
elem14_o <= "01110110110000";
elem15_o <= "01110111010000";
elem16_o <= "01110111110000";
elem17_o <= "01111000010000";
elem18_o <= "01111000110000";
elem19_o <= "01110011101101";
elem20_o <= "01110100001100";
when 2 =>
elem01_o <= "00010000010010";
when others =>
elem01_o <= "00100001010000";
elem02_o <= "11111001010000";
end case;
end process processLevel;
----------------------
-- nextLevel Logic
----------------------
processNextLevel : process (clk_i, reset_i)
begin
if (reset_i = '1') then
currentLevel_s <= 0;
elsif rising_edge(clk_i) then
if (nextLevel_i = '1') then
currentLevel_s <= currentLevel_s + 1;
end if;
end if;
end process processNextLevel;
end Behavioral;
Note: currentLevel_s is declared as follow:
signal currentLevel_s : integer range 0 to 127 := 0;
I have then launched the synthesis and I get the following results:
I think this result occurs because I do not affect a value to currentLevel_s (no else clause after the if (reset_i = '1') then). I simply want to keep the current value if the condition is not filled.
Any ideas how to solve these warnings ?
This is an easy one:
You only do something when currentLevel_s is 1 ("01") or 2 ("10"). All other values don't matter. The synthesis tool optimizes away all other values.
Try adding when 127 => [something].
Or just
signal currentLevel_s : integer range 0 to 3 := 0;
if nextLevel_i = '1' and currentLevel_s < 3 then
currentLevel_s <= currentLevel_s + 1;
end if;
Hello I'm trying to create a 32-bit adder with a few opcodes and I've got it working quite well except for two cases and I can't seem to find what's causing them.. Maybe you can help me?
The subtraction case always fails for some reason and the ADDC case fails to compute the correct output when it should be using the carry bit in c_reg that has been created by the ADDS operation.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ALU IS
GENERIC(WIDTH : NATURAL := 32);
PORT(Clk : IN STD_LOGIC := '0';
Reset : IN STD_LOGIC := '0';
A : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (OTHERS => '0');
B : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (OTHERS => '0');
Op : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
Outs : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0));
END ALU;
ARCHITECTURE arch_ALU OF ALU IS
COMPONENT adder
PORT(OpA : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
OpB : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
Cin : IN STD_LOGIC;
Cout : OUT STD_LOGIC;
Result : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0));
END COMPONENT;
SIGNAL adder_output : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL B_neg : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL c_flag : STD_LOGIC := '0';
SIGNAL c_reg : STD_LOGIC := '0';
SIGNAL cin : STD_LOGIC := '0';
BEGIN
adder_comp : adder
PORT MAP(OpA => A,
OpB => B_neg,
Cin => cin,
Result => adder_output,
Cout => c_flag);
WITH Op SELECT
B_neg <= NOT(B) WHEN "1000",
B WHEN OTHERS;
WITH Op SELECT
cin <= '1' WHEN "1000", -- SUB
c_reg WHEN "0111", -- ADDC
'0' WHEN OTHERS; -- ADD/ADDS
ALU_Process:
PROCESS(Clk)
BEGIN
IF Reset = '0' THEN
Outs <= (OTHERS => '0');
ELSIF rising_edge(Clk) THEN
CASE Op IS
WHEN "0001" => Outs <= A AND B;
WHEN "0010" => Outs <= A OR B;
WHEN "0011" => Outs <= A NOR B;
WHEN "0100" => Outs <= A XOR B;
WHEN "0101" => Outs <= adder_output; -- ADD
WHEN "0110" => Outs <= adder_output; -- ADDS
c_reg <= c_flag;
WHEN "0111" => Outs <= adder_output; -- ADDC
WHEN "1000" => Outs <= adder_output; -- SUB
WHEN "1001" => Outs <= STD_LOGIC_VECTOR(UNSIGNED(A) SLL to_integer(UNSIGNED(B(4 DOWNTO 0))));
WHEN "1010" => Outs <= STD_LOGIC_VECTOR(unsigned(A) SRL to_integer(UNSIGNED(B(4 DOWNTO 0))));
WHEN "1011" => Outs <= STD_LOGIC_VECTOR(shift_right(SIGNED(A),to_integer(UNSIGNED(B(4 DOWNTO 0)))));
WHEN OTHERS => Outs <= (OTHERS => '0');
END CASE;
END IF;
END PROCESS;
END arch_ALU;
Only the ADDS operation should write it's carry-out to the c_reg and ADDC operation should take the c_reg into account when calculating it's output
The adder is tested and working correctly so the problem is not in the adder design.
First of all I'd like to get to know the problem of the subtraction because it is doing subtraction but the result is a little bit off.. For example:
A : h'E6A4960F
B : h'7B494E34
Op : d'1000
Outs: h'6B5B47DA while it should be h'6B5B47DB
A : h'EFDE31A3
B : h'0BCAB8FA
Op : d'1000
Out : h'E41378BB while should be h'E41378A9
Can you spot my misstake? Cause I certainly can't..
While you didn't provide a Minimal, Complete, and Verifiable example the reader can at least test the subtract portions of your design that are present:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
generic (width: natural := 32);
port (
clk: in std_logic := '0';
reset: in std_logic := '0';
a: in std_logic_vector(width - 1 downto 0) := (others => '0');
b: in std_logic_vector(width - 1 downto 0) := (others => '0');
op: in std_logic_vector(3 downto 0) := (others => '0');
outs: out std_logic_vector(width - 1 downto 0)
);
end alu;
architecture arch_alu of alu is
-- component adder
-- port (
-- opa: in std_logic_vector(width - 1 downto 0);
-- opb: in std_logic_vector(width - 1 downto 0);
-- cin: in std_logic;
-- cout: out std_logic;
-- result: out std_logic_vector(width - 1 downto 0)
-- );
-- end component;
procedure adder (
signal opa: in std_logic_vector(width - 1 downto 0);
signal opb: in std_logic_vector(width - 1 downto 0);
signal cin: in std_logic;
signal cout: out std_logic;
signal result: out std_logic_vector(width - 1 downto 0)
) is
variable sum: unsigned (width downto 0);
begin
sum := unsigned('0' & opa) + unsigned(opb) + unsigned'(""& cin);
result <= std_logic_vector(sum (width - 1 downto 0));
cout <= sum(width);
end procedure;
signal adder_output: std_logic_vector(width - 1 downto 0) := (others => '0');
signal b_neg: std_logic_vector(width - 1 downto 0) := (others => '0');
signal c_flag: std_logic := '0';
signal c_reg: std_logic := '0';
signal cin: std_logic := '0';
begin
adder_comp:
adder
-- port map (
(
opa => a,
opb => b_neg,
cin => cin,
result => adder_output,
cout => c_flag
);
with op select
b_neg <= not b when "1000",
b when others;
with op select
cin <= '1' when "1000", -- sub
c_reg when "0111", -- addc
'0' when others; -- add/adds
alu_process:
process(clk)
begin
if reset = '0' then
outs <= (others => '0');
elsif rising_edge(clk) then
case op is
when "0001" => outs <= a and b;
when "0010" => outs <= a or b;
when "0011" => outs <= a nor b;
when "0100" => outs <= a xor b;
when "0101" => outs <= adder_output; -- add
when "0110" => outs <= adder_output; -- adds
c_reg <= c_flag;
when "0111" => outs <= adder_output; -- addc
when "1000" => outs <= adder_output; -- sub
when "1001" => outs <= std_logic_vector (
unsigned(a) sll to_integer(unsigned(b(4 downto 0)))
);
when "1010" => outs <= std_logic_vector (
unsigned(a) srl to_integer(unsigned(b(4 downto 0)))
);
when "1011" => outs <= std_logic_vector (
shift_right(signed(a),to_integer(unsigned(b(4 downto 0))))
);
when others => outs <= (others => '0');
end case;
end if;
end process;
end arch_alu;
library ieee;
use ieee.std_logic_1164.all;
entity alu_tb is
end entity;
architecture foo of alu_tb is
constant width: integer := 32;
signal clk: std_logic := '0';
signal reset: std_logic := '0';
signal a: std_logic_vector(width - 1 downto 0) := (others => '0');
signal b: std_logic_vector(width - 1 downto 0) := (others => '0');
signal op: std_logic_vector(3 downto 0) := (others => '0');
signal outs: std_logic_vector(width - 1 downto 0);
begin
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if Now > 90 ns then
wait;
end if;
end process;
DUT:
entity work.alu
port map (
clk => clk,
reset => reset,
a => a,
b => b,
op => op,
outs => outs
);
STIMULUS:
process
begin
wait for 20 ns;
reset <= '1';
a <= x"E6A4960F";
b <= x"7B494E34";
op <= "1000";
wait for 20 ns;
a <= x"EFDE31A3";
b <= x"0BCAB8FA";
wait for 20 ns;
wait;
end process;
end architecture;
I wrote a quick and dirty procedure adder. This eliminates your adder entity/architecture and the component declaration.
I added a simple testbench for the two subtractions, this eliminates your test bench or testing procedure.
And this gives:
And as you can see the results are what you claim as correct.
So what that leaves is either your adder or your testbench (it's a stretch to blame your component declaration).
So what we get from this is that you haven't presented enough information to determine where the error is.
I did this little demonstration because the two errors don't have all the wrong bits in common. If you've tested your adder and are sure of it, it's probably the stimulus input when subtracting.
I want to make a FSM model of FIR, for that I need to write FIR calculation code line in FSM implementation.
Here is the actual and correct code for FIR
entity fir_4tap is
port( Clk : in std_logic; --clock signal
Clk_fast : in std_logic;
-- Xin : in signed(7 downto 0); --input signal
bit_in : in std_logic;
bit_out : out std_logic;
Yout : out signed(15 downto 0) --filter output
);
end fir_4tap;
architecture Behavioral of fir_4tap is
signal add_out3 : signed(15 downto 0) := (others => '0');
signal index : unsigned(2 downto 0) := (others =>'0');
signal counter : unsigned(3 downto 0) := (others => '0');
signal p : unsigned(1 downto 0) := (others => '0');
signal k : unsigned(1 downto 0) := (others => '0');
signal j : unsigned(1 downto 0) := (others => '0');
type array_signed is array(8 downto 0) of signed(7 downto 0);
signal z : array_signed := (others => "00000000");
type array_signed1 is array(3 downto 0) of signed(7 downto 0);
signal H : array_signed1 := (others => "00000000");
signal Xin : array_signed1 := (others => "00000000");
begin
z(0) <= to_signed(-3,8);
z(1) <= to_signed(1,8);
z(2) <= to_signed(0,8);
z(3) <= to_signed(-2,8);
z(4) <= to_signed(-1,8);
z(5) <= to_signed(4,8);
z(6) <= to_signed(-5,8);
z(7) <= to_signed(6,8);
z(8) <= to_signed(0,8);
H(0) <= to_signed(-2,8);
H(1) <= to_signed(-1,8);
H(2) <= to_signed(3,8);
H(3) <= to_signed(4,8);
process (clk)
begin
if (rising_edge(Clk)) then
index <= index +1;
if (index = "111") then
Xin(to_integer(p)) <= z(to_integer(counter)); k <= p;
p <= p + 1;
***-- This part of the code has problem, I want to write the line which is summing --up for add_out3 in a for loop.***
add_out3 <= (others => '0');
add_out3 <= Xin(to_integer(k))*H(to_integer(j)) + Xin(to_integer(k-1))*H(to_integer(j+1)) + Xin(to_integer(k-2))*H(to_integer(j+2)) + Xin(to_integer(k-3))*H(to_integer(j+3));
Yout <= add_out3;
end if;
end if;
end process;
end Behavioral;
Now Below is the FSM implementation try by me but not getting the same out sample as input can somebody tell me what could be the problem in the code?
----------------FSM implementation of the FIR filter ----------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity test is
port( Clk : in std_logic; --clock signal
Clk_fast : in std_logic;
bit_in : in std_logic;
bit_out : out std_logic;
Yout : out signed(15 downto 0) --filter output
);
end test;
architecture Behavioral of test is
signal data_buffer : signed(7 downto 0) := (others => '0');
signal index : unsigned(2 downto 0) := (others =>'0');
signal counter : unsigned(3 downto 0) := (others => '0');
type array_signed is array(8 downto 0) of signed(7 downto 0);
signal z : array_signed := (others => "00000000");
type array_signed1 is array(3 downto 0) of signed(7 downto 0);
signal H : array_signed1 := (others => "00000000");
signal input : signed(7 downto 0) := (others => '0');
type MULT_TYPE is array(3 downto 0) of signed(15 downto 0);
signal MULT_array : MULT_TYPE := (others => "0000000000000000");
type ADD_TYPE is array(3 downto 0) of signed(15 downto 0);
signal ADD_array : ADD_TYPE := (others => "0000000000000000");
constant ZERO : signed(15 downto 0) := (others => '0');
type state_type is (s0,s1,s2,s3); --type of state machine.
signal current_s : state_type := s0; --current and next state declaration.
signal next_s : state_type := s0;
signal reset : std_logic := '0';
signal go : std_logic := '0';
signal change_state : std_logic := '0' ;
signal counter_FSM_monitor : unsigned( 6 downto 0) := "0000000";
begin
z(0) <= to_signed(-3,8);
z(1) <= to_signed(1,8);
z(2) <= to_signed(0,8);
z(3) <= to_signed(-2,8);
z(4) <= to_signed(-1,8);
z(5) <= to_signed(4,8);
z(6) <= to_signed(-5,8);
z(7) <= to_signed(6,8);
z(8) <= to_signed(0,8);
H(0) <= to_signed(-2,8);
H(1) <= to_signed(-1,8);
H(2) <= to_signed(3,8);
H(3) <= to_signed(4,8);
process (Clk) is
begin
if falling_edge(Clk) then
data_buffer(to_integer(index)) <= bit_in;
index <= index +1;
if (index = "111") then
input <= z(to_integer(counter));
counter <= counter + 1;
if(counter = "1000") then
counter <= "0000";
end if;
end if;
end if;
end process;
process (clk_fast)
begin
if (falling_edge(clk_fast)) then
counter_FSM_monitor <= counter_FSM_monitor + 1;
if( to_integer(counter_FSM_monitor) = 76) then
counter_FSM_monitor <= "0000000";
end if;
case change_state is
when '1' =>
current_s <= next_s; --state change.
when '0' => --current_s <= s0;
when others =>
end case;
end if;
end process;
Process(current_s,input)
begin
if ( to_integer(counter_FSM_monitor) < 64 ) then
-- waiting for the Input
elsif (to_integer(counter_FSM_monitor) >= 64 and to_integer(counter_FSM_monitor) < 76) then
---------------------------------------------- FSM ----------------------------------------
case current_s is
when s0 =>
mult_array(0) <= input*H(3);
ADD_array(0) <= ZERO + mult_array(0);
next_s <= s1;
change_state <= '1';
when s1 =>
mult_array(1) <= input*H(2);
ADD_array(1) <= mult_array(1) + ADD_array(0);
next_s <= s2;
change_state <= '1';
when s2 =>
mult_array(2) <= input*H(1);
ADD_array(2) <= mult_array(2) + ADD_array(1);
next_s <= s3;
change_state <= '1';
when s3 =>
mult_array(3) <= input*H(0);
ADD_array(3) <= mult_array(3) + ADD_array(2);
Yout <= ADD_array(3);
next_s <= s0;
change_state <= '1';
when others =>
next_s <= s0;-- never comes here
change_state <= '1';
end case;
---------------------------------------------- FSM ----------------------------------------
end if;
end process;
end Behavioral;
How ever I am not able to receive the same output which I received by the first code.
FSM code gives the correct output for the first out but from the second out sample it gives wrong result.Can somebody tell me what I am doing wrong ?
This answer is for the initial version of the question but Now question has been changed.
Made add_out3 a variable instead of a signal.
for i in 0 to 3 loop
add_out3 := add_out3 + Xin(k-i)*H(i);
end loop;
Did the above changes in the for loop It works fine.
So the code in my question is a correct code for FIR also, works smoothly.
Learnt that one needs to be very careful while using signal or variables. All the signals get a new value at the same time i.e at the end of clock period, while in variables values gets updated as assigned within a process. Tried to run the simulation step by step and figured out the problem.