VHDL Aggregate Assignment Using Aliases - vhdl

Question

I am having some trouble using aggregates in my VHDL test bench (short hand shown below).
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all
entity TB is
end entity;
architecture RTL of TB is
-- constant(s)
constant CLK_PERIOD : time := 10 ns; -- 100 MHz
-- signal(s)
signal CLK : std_logic := '0';
signal nRST : std_logic := '1';
signal CONFIG_REG : std_logic_vector(7 downto 0) := (others => '0');
begin
-- clock driver
CLK <= NOT CLK after (CLK_PERIOD / 2.0);
-- main process
process
begin
-- reset driver...
nRST <=
'1',
'0' after (CLK_PERIOD * 1);
-- set initial configuration...
CONFIG_REG <= (
6 => '1',
3 downto 2 => "01",
7 | 0 => '1',
others => '0'
);
-- do test-bench stuff...
-- update configuration...
CONFIG_REG <= (
6 => '0',
3 downto 2 => "10",
7 | 0 => '1',
others => '0'
);
-- do more test-bench stuff...
end process;
end architecture;
I really want to 'name' the parts of the configuration register so that it actually reads well.
So I want to say:
Bit[6] = ENABLE
Bit[3:2] = MODE
Bit[7|0] = READY_DONE
I know that I can use a constant for the 6:
constant ENABLE : integer := 6;
and then my code looks like this:
CONFIG_REG <= (
ENABLE => '1',
3 downto 2 => "01",
7 | 0 => '1',
others => '0'
);
But I've been stumped to try and get the range 3 downto 2 and the 7|0 named so that the code looks like:
CONFIG_REG <= (
ENABLE => '1',
MODE => "01",
READY_DONE => '1',
others => '0'
);
I thought I might be able to accomplish this using aliasing and I've been looking at the VHDL Golden Reference Guide (p.15) which has been pretty helpful as far as understanding aliasing and ranges go, but I still cannot figure out how to name a range itself or an 'or'(|) of values.
Currently I have the below 'hack', which I'm not really fond of...
constant ENABLE : integer := 6;
alias MODE is CONFIG_REG(3 downto 2);
-- what to do about the OR though???
CONFIG_REG <= (
ENABLE => '1',
MODE'RANGE => "01",
7 | 0 => '1',
others => '0'
);
I really want to make my test-bench readable so that when I look at it 6 mo. from now, I'll know what it's doing without having to go and figure out "Now what was bit[6] again???" or in the event I have to hand off my code to another developer, they can easily get an idea of what I was trying to accomplish.
Any help / advice would be appreciated on how to do this.
Thanks for reading.
EDIT: Fixed the 7 | 0 to be valid:
Invalid:
7 | 0 => "10",
Valid:
7 | 0 => '1',

Answer 1

Beware, your code is not valid: the aggregate notation 7 | 0 stands for groups of indices, not vectors. It should be associated std_logic values, not std_logic_vector. Moreover, in VHDL versions prior 2008, the aggregate notation 3 downto 2 should also be associated std_logic values:
-- set initial configuration...
CONFIG_REG <= (
6 => '1',
3 downto 2 => '1',
7 | 0 => '0',
others => '0'
);
In VHDL 2008 the association between choices that are discrete ranges and expressions of the type of the aggregate are now supported. So, the 3 downto 2 => "01" is OK in VHDL 2008. But as VHDL 2008 is still not fully supported by many synthesizers, you should probably be careful, unless this code is not supposed to be synthesized, of course.
Anyway, using records instead of vectors could be an option for your problem. And in case you also need a vector version of the data, you could very easily write conversion functions between vector and record types. Example:
package foo is
type config_type is record
ready: std_ulogic;
enable: std_ulogic;
foobar: std_ulogic_vector(1 downto 0);
mode: std_ulogic_vector(1 downto 0);
reserved: std_ulogic;
done: std_ulogic;
end record;
function rec2vec(v: config_type) return std_ulogic_vector;
function vec2rec(v: std_ulogic_vector) return config_type;
end package foo;
package body foo is
function rec2vec(v: config_type) return std_ulogic_vector is
begin
return v.ready & v.enable & v.foobar & v.mode & v.reserved & v.done;
end function rec2vec;
function vec2rec(v: std_ulogic_vector) return config_type is
constant vv: std_ulogic_vector(7 downto 0) := v;
begin
return (ready => vv(7), enable => vv(6), foobar => vv(5 downto 4),
mode => vv(3 downto 2), reserved => vv(1), done => vv(0));
end function vec2rec;
end package body foo;
You could then use the aggregate notation to assign records:
signal config_reg: config_type;
...
config_reg <= (
ready => '1',
enable => '1',
foobar => "--",
mode => "01",
others => '0'
);
And convert to-from vectors:
signal config_reg_v: std_ulogic_vector(7 downto 0);
...
config_reg_v <= rec2vec(config_reg);
...
config_reg <= vec2rec(config_reg_v);
...
config_reg <= vec2rec(X"ff");
Note: I used std_ulogic and std_ulogic_vector instead of the resolved std_logic and std_logic_vector. There are good reasons for that but it is another question.

Answer 2

I prefer to define full width constants in my package:
subtype ConfigRegType is std_logic_vector(7 downto 0) ;
constant CFG_ENABLE : ConfigRegType := B"0_1_000000" ;
constant CFG_MODE0 : ConfigRegType := B"0000_00_00" ;
constant CFG_MODE1 : ConfigRegType := B"0000_00_00" ;
constant CFG_MODE2 : ConfigRegType := B"0000_10_00" ;
constant CFG_MODE3 : ConfigRegType := B"0000_11_00" ;
constant CFG_READY : ConfigRegType := B"1_0000000" ;
constant CFG_DONE : ConfigRegType := B"0000000_1" ;
. . .
Now when you are ready to write to it, simply "or" the value set you want:
CONFIG_REG <= CFG_ENABLE or CFG_MODE1 or CFG_READY or CFG_DONE ;
I have played with other ways, however, like you are noting they seem to require knowledge of details of the implementation.