I'm trying to modify variable inside 2nd-level target foo (Option 2). I'd expect output to be a b c, but I see a c, i.e., VAR += b is never executed. It behaves as if VAR is local for all target. But at the same time with Option 1, I see that b is appended into VAR. I suspect it is caused by := assignment in the target, but I couldn't find anything specific about that.
VAR = a
all: VAR += b
all: foo
# Option 1. with this line output is "a b z"
# foo: VAR += z
# Option 2. with this line output is "a c"
# foo: VAR := $(VAR) c
foo:
#echo $(VAR)
The explanation is that expressions with := assignments in target specific variables are evaluated by Make right at the time of reading the makefile and not when executing recipes for targets.
This seems to be not explained at all in the corresponding chapter of Make manual
Related
I am working on a C++ library where I am following the structure below:
ROOTDIR = ~/path/to/proj
BLDDIR = $(ROOTDIR)/build
INCDIR = $(ROOTDIR)/include
SRCDIR = $(ROOTDIR)/src
LIBSRCDIR = $(SRCDIR)/lib
TESTSRCDIR = $(SRCDIR)/test
OBJDIR = $(ROOTDIR)/obj
LIBOBJDIR = $(OBJDIR)/lib
TESTOBJDIR = $(OBJDIR)/test
LIBDIR = $(ROOTDIR)/lib
BINDIR = $(ROOTDIR)/bin
And the file definitions are:
MKFILE = $(BLDDIR)/Makefile
HDRFILES = $(wildcard $(INCDIR)/*.hpp)
LIBSRCFILES := $(wildcard $(LIBSRCDIR)/*.cpp)
TESTSRC = $(TESTSCRCDIR)/test.cpp
LIBOBJFILES := $(patsubst $(LIBSRCDIR)/%.cpp, $(LIBOBJDIR)/%.o, $(LIBSRCFILES))
TESTOBJ := $(TESTOBJDIR)/test.o
LIBFILE = $(LIBDIR)/$(NAME)-$(VERSION).a
TESTFILE = $(BINDIR)/test
ZIPFILE = $(ROOTDIR)/$(NAME).$(VERSION).zip
I have tested & confirmed that everything works, but for some reason $(TESTSRC) is printing empty even though Make is able to set $(TESTOBJ). I tried setting up the variable definitions in the hierarchy to ensure everything is generated in level, but that one variable remains empty.
EDIT 1:
Make is finding all of the directories properly
I have made sure that the file extension is correct
The variable is not being overwritten
EDIT 2:
The specific error I"mg getting is:
make: *** No rule to make target /test.cpp', needed by ..../test.o
..../test.o is in the right directory & defined separately without being dependent on a patsubst like the libsrc.
Read carefully:
TESTSRCDIR = $(SRCDIR)/test
^^^
and:
TESTSRC = $(TESTSCRCDIR)/test.cpp
^^^
This is a simple Makefile:
...
VAR :=
FLAGS := --flag=$(VAR)
target_1: VAR = 1
target_1: $(DEPS_1)
$(CMD) $(FLAGS)
...
target_2: VAR = 2
target_2: $(DEPS_2)
$(CMD) $(FLAGS)
...
I want to reassign variable VAR to make make recalculate value of FLAGS to use it for different targets, is there a way to do something like this?
Don't use simple expansion for FLAGS:
FLAGS := --flag=$(VAR)
is wrong; you want this:
FLAGS = --flag=$(VAR)
If you expand FLAGS immediately, the all the variables are expanded to whatever their value is at that point in the makefile. There is no opportunity to redo that later, because the variable reference is gone: it's replaced with the value.
I have issues assigning the same variable multiple times in Makefile.
I am making a kind of modular makefile where I only deal with components instead of every source file and include directory.
This first solution works fine
MainRootDir = Components/Main
include $(RootDir)/$(MainRootDir)/Main.mak
Debug_Includes += $(addprefix $(MainRootDir)/,$(Main_Includes))
Debug_ASM_Sources += $(addprefix $(MainRootDir)/,$(Main_ASM_Static))
Debug_CC_Sources += $(addprefix $(MainRootDir)/,$(Main_CC_Static))
Debug_ASM_Sources += $(addprefix $(CfgDir)/, $(Main_ASM_Config))
Debug_CC_Sources += $(addprefix $(CfgDir)/, $(Main_CC_Config))
AdderRootDir = Components/Adder
include $(RootDir)/$(AdderRootDir)/Adder.mak
Debug_Includes += $(addprefix $(AdderRootDir)/,$(Adder_Includes))
Debug_ASM_Sources += $(addprefix $(AdderRootDir)/,$(Adder_ASM_Static))
Debug_CC_Sources += $(addprefix $(AdderRootDir)/,$(Adder_CC_Static))
Debug_ASM_Sources += $(addprefix $(CfgDir)/, $(Adder_ASM_Config))
Debug_CC_Sources += $(addprefix $(CfgDir)/, $(Adder_CC_Config))
However, if I try to standardize the block by defining variables and Re-Assigning new value before adding the software component each time, it stops working:
SwcName = Main
SwcRootDir = Components/$(SwcName)
include $(RootDir)/$(SwcRootDir)/$(SwcName).mak
Debug_Includes += $(addprefix $(SwcRootDir)/,$($(SwcName)_Includes))
Debug_ASM_Sources += $(addprefix $(SwcRootDir)/,$($(SwcName)_ASM_Static))
Debug_CC_Sources += $(addprefix $(SwcRootDir)/,$($(SwcName)_CC_Static))
Debug_ASM_Sources += $(addprefix $(CfgDir)/, $($(SwcName)_ASM_Config))
Debug_CC_Sources += $(addprefix $(CfgDir)/, $($(SwcName)_CC_Config))
SwcName = Adder
SwcRootDir = Components/$(SwcName)
include $(RootDir)/$(SwcRootDir)/$(SwcName).mak
Debug_Includes += $(addprefix $(SwcRootDir)/,$($(SwcName)_Includes))
Debug_ASM_Sources += $(addprefix $(SwcRootDir)/,$($(SwcName)_ASM_Static))
Debug_CC_Sources += $(addprefix $(SwcRootDir)/,$($(SwcName)_CC_Static))
Debug_ASM_Sources += $(addprefix $(CfgDir)/, $($(SwcName)_ASM_Config))
Debug_CC_Sources += $(addprefix $(CfgDir)/, $($(SwcName)_CC_Config))
The issue is that the source files of component Main are defined multiple times.
As if the Adder block is also expanding SwcName with the value Main.
Any idea how to prevent this?
You are using recursively expanded variables (var = ...), which is the default. So make defers the evaluation of the right hand side of your assignments until the variable's value is really needed. Example:
a = 1
b += $(a)
a = 2
b += $(a)
.PHONY: all
all:
#echo $(b)
will print 2 2 instead of the 1 2 you expect because what make actually stored in variable b was $(a) $(a), which it evaluated only before passing the recipe of all to the shell. And at that time a has only one single value: the last one it has been assigned, that is, 2.
You could use simply expanded variables (var := ...), instead:
b :=
a := 1
b += $(a)
a := 2
b += $(a)
.PHONY: all
all:
#echo $(b)
which will print 1 2. Do not forget the apparently useless b :=: it tells make that b is not a recursively expanded variable but a simply expanded one. Different from the default form, the value assigned to a simply expanded variable is evaluated when it is defined, its expansion is not deferred until the variable's value is needed.
But repeating large portions of code as in what you show is not optimal. Indeed, repeating things is frequently needed with humans but almost never optimal with computers. If you are using GNU make, as suggested by tripleee, you could use a kind of user-defined function:
Debug_Includes :=
Debug_ASM_Sources :=
...
# $(1) is the current SwcName
define MY_FUNC
SwcRootDir := Components/$(1)
include $$(RootDir)/$$(SwcRootDir)/$$(1).mak
Debug_Includes += $$(addprefix $$(SwcRootDir)/,$$($(1)_Includes))
Debug_ASM_Sources += $$(addprefix $$(SwcRootDir)/,$$($$(1)_ASM_Static))
...
endef
and then:
$(foreach SwcName,Main Adder,$(eval $(call MY_FUNC,$(SwcName))))
Do not forget the $$ in the macro definition. They are needed. See the GNU make manual for the full explanation.
This is a matter of recursive vs simply expanded variables. I'm going to guess that Debug_Includes is not initialized with a := earlier on, which means it defaults to be a recursively expanded variable. Therefore it is set to $(RootDir)/$(SwcRootDir)/$(SwcName).mak, and the internal variables are only expanded when it is referenced (at which point SwcRootDir will be Components/$(SwcName)).
Try initializing your variables with := at the top of your file to make them simple. Then they will be assigned values right away, and the internal variables will be set to what they were at the time of the definition.
I'm trying to have rule that if VAR ends with ENDS_WITH it does X else it does Y. Now, I was able to kinda achieve this with the following:
VAR := Hello, World
ENDS_WITH := rld
endswith:
ifeq ($(findstring $(ENDS_WITH)potato,$(VAR)potato),)
#echo "$(VAR) doesn't end with $(ENDS_WITH)"
# Do X
else
#echo "$(VAR) ends with $(ENDS_WITH)"
# Do Y
endif
However, this assumes neither string contains potato otherwise it will have strange behavior. (Also it's kinda a hack)
What would be the correct way to go about achieving this?
You can use this:
$(patsubst %$(ENDS_WITH),,$(lastword $(VAR)))
This will expand to an empty string if VAR ends with the value of the variable ENDS_WITH, else the non-empty string. We have to use lastword here because patsubst works on each word individually but we only care about the last one.
So:
endswith:
ifeq ($(patsubst %$(ENDS_WITH),,$(lastword $(VAR))),)
#echo "$(VAR) ends with $(ENDS_WITH)"
# Do Y
else
#echo "$(VAR) doesn't end with $(ENDS_WITH)"
# Do X
endif
I have a makefile which takes a TYPE parameter and runs a test file using that name. Otherwise it takes all the test files.
ifneq (,$(TYPE))
TEST_SRCS := $(wildcard test/$(TYPE)Test.cpp)
else
TEST_SRCS := $(wildcard test/*Test.cpp)
endif
print:
echo $(TEST_SRCS)
This works fine If I execute like,
make TYPE=Add
But Now I want to give more than one value to TYPE So that it should take both AddTest.cpp and SubtractTest.cpp
e.g.
make TYPE=Add,Subtract
I have tried $(foreach var,$(TYPE), TEST_FILES += var)
Make isn't good at this kind of manipulation, but you can break a comma-separated list into a space-separated list like this:
COMMA = ,
TYPE_LIST = $(subst $(COMMA), ,$(TYPE))
Then you can apply your wildcard logic like this:
FILE_LIST = $(patsubst %,test/%Test.cpp,$(TYPE_LIST))
TEST_SRCS := $(wildcard $(FILE_LIST))