Makefile variable printing empty despite definition structure - makefile

I am working on a C++ library where I am following the structure below:
ROOTDIR = ~/path/to/proj
INCDIR = $(ROOTDIR)/include
And the file definitions are:
MKFILE = $(BLDDIR)/Makefile
HDRFILES = $(wildcard $(INCDIR)/*.hpp)
LIBSRCFILES := $(wildcard $(LIBSRCDIR)/*.cpp)
I have tested & confirmed that everything works, but for some reason $(TESTSRC) is printing empty even though Make is able to set $(TESTOBJ). I tried setting up the variable definitions in the hierarchy to ensure everything is generated in level, but that one variable remains empty.
Make is finding all of the directories properly
I have made sure that the file extension is correct
The variable is not being overwritten
The specific error I"mg getting is:
make: *** No rule to make target /test.cpp', needed by ..../test.o
..../test.o is in the right directory & defined separately without being dependent on a patsubst like the libsrc.

Read carefully:


GNU Make: Remove string from array with subdirectories if string contains "dirToExclude"

I have a directory with a lot of subdirectories which are containing source-files. Therefore I am looking in every subdirectoy for .c-files: cSources = $(shell dir /s /b *.c)
However there are subdirectories with source-files I do not want to compile. If I have a variable dirToExclude = dirName how can I remove every string in cSources that contains 'dirName'?
I know that there is the findstring-function. But I can't figure out how to use findstring on every string in the array. I am looking for some way to get a nested loop like (pseudo code):
foreach (var in cSources)
if (var.contains(dirToExclude))
cSources -= var
If you know dirToExclude is always at the beginning of the string you can just write:
cSources := $(filter-out $(dirToExclude)%,$(cSources))
If you want to remove any filename where the string appears anywhere, you can use:
cSources := $(foreach S,$(cSources),$(if $(findstring $(dirToExclude),$(S)),,$(S)))

Makefile issue with multiple variable assignment

I have issues assigning the same variable multiple times in Makefile.
I am making a kind of modular makefile where I only deal with components instead of every source file and include directory.
This first solution works fine
MainRootDir = Components/Main
include $(RootDir)/$(MainRootDir)/Main.mak
Debug_Includes += $(addprefix $(MainRootDir)/,$(Main_Includes))
Debug_ASM_Sources += $(addprefix $(MainRootDir)/,$(Main_ASM_Static))
Debug_CC_Sources += $(addprefix $(MainRootDir)/,$(Main_CC_Static))
Debug_ASM_Sources += $(addprefix $(CfgDir)/, $(Main_ASM_Config))
Debug_CC_Sources += $(addprefix $(CfgDir)/, $(Main_CC_Config))
AdderRootDir = Components/Adder
include $(RootDir)/$(AdderRootDir)/Adder.mak
Debug_Includes += $(addprefix $(AdderRootDir)/,$(Adder_Includes))
Debug_ASM_Sources += $(addprefix $(AdderRootDir)/,$(Adder_ASM_Static))
Debug_CC_Sources += $(addprefix $(AdderRootDir)/,$(Adder_CC_Static))
Debug_ASM_Sources += $(addprefix $(CfgDir)/, $(Adder_ASM_Config))
Debug_CC_Sources += $(addprefix $(CfgDir)/, $(Adder_CC_Config))
However, if I try to standardize the block by defining variables and Re-Assigning new value before adding the software component each time, it stops working:
SwcName = Main
SwcRootDir = Components/$(SwcName)
include $(RootDir)/$(SwcRootDir)/$(SwcName).mak
Debug_Includes += $(addprefix $(SwcRootDir)/,$($(SwcName)_Includes))
Debug_ASM_Sources += $(addprefix $(SwcRootDir)/,$($(SwcName)_ASM_Static))
Debug_CC_Sources += $(addprefix $(SwcRootDir)/,$($(SwcName)_CC_Static))
Debug_ASM_Sources += $(addprefix $(CfgDir)/, $($(SwcName)_ASM_Config))
Debug_CC_Sources += $(addprefix $(CfgDir)/, $($(SwcName)_CC_Config))
SwcName = Adder
SwcRootDir = Components/$(SwcName)
include $(RootDir)/$(SwcRootDir)/$(SwcName).mak
Debug_Includes += $(addprefix $(SwcRootDir)/,$($(SwcName)_Includes))
Debug_ASM_Sources += $(addprefix $(SwcRootDir)/,$($(SwcName)_ASM_Static))
Debug_CC_Sources += $(addprefix $(SwcRootDir)/,$($(SwcName)_CC_Static))
Debug_ASM_Sources += $(addprefix $(CfgDir)/, $($(SwcName)_ASM_Config))
Debug_CC_Sources += $(addprefix $(CfgDir)/, $($(SwcName)_CC_Config))
The issue is that the source files of component Main are defined multiple times.
As if the Adder block is also expanding SwcName with the value Main.
Any idea how to prevent this?
You are using recursively expanded variables (var = ...), which is the default. So make defers the evaluation of the right hand side of your assignments until the variable's value is really needed. Example:
a = 1
b += $(a)
a = 2
b += $(a)
.PHONY: all
#echo $(b)
will print 2 2 instead of the 1 2 you expect because what make actually stored in variable b was $(a) $(a), which it evaluated only before passing the recipe of all to the shell. And at that time a has only one single value: the last one it has been assigned, that is, 2.
You could use simply expanded variables (var := ...), instead:
b :=
a := 1
b += $(a)
a := 2
b += $(a)
.PHONY: all
#echo $(b)
which will print 1 2. Do not forget the apparently useless b :=: it tells make that b is not a recursively expanded variable but a simply expanded one. Different from the default form, the value assigned to a simply expanded variable is evaluated when it is defined, its expansion is not deferred until the variable's value is needed.
But repeating large portions of code as in what you show is not optimal. Indeed, repeating things is frequently needed with humans but almost never optimal with computers. If you are using GNU make, as suggested by tripleee, you could use a kind of user-defined function:
Debug_Includes :=
Debug_ASM_Sources :=
# $(1) is the current SwcName
define MY_FUNC
SwcRootDir := Components/$(1)
include $$(RootDir)/$$(SwcRootDir)/$$(1).mak
Debug_Includes += $$(addprefix $$(SwcRootDir)/,$$($(1)_Includes))
Debug_ASM_Sources += $$(addprefix $$(SwcRootDir)/,$$($$(1)_ASM_Static))
and then:
$(foreach SwcName,Main Adder,$(eval $(call MY_FUNC,$(SwcName))))
Do not forget the $$ in the macro definition. They are needed. See the GNU make manual for the full explanation.
This is a matter of recursive vs simply expanded variables. I'm going to guess that Debug_Includes is not initialized with a := earlier on, which means it defaults to be a recursively expanded variable. Therefore it is set to $(RootDir)/$(SwcRootDir)/$(SwcName).mak, and the internal variables are only expanded when it is referenced (at which point SwcRootDir will be Components/$(SwcName)).
Try initializing your variables with := at the top of your file to make them simple. Then they will be assigned values right away, and the internal variables will be set to what they were at the time of the definition.

Target-specific assignments in Makefile

I'm trying to modify variable inside 2nd-level target foo (Option 2). I'd expect output to be a b c, but I see a c, i.e., VAR += b is never executed. It behaves as if VAR is local for all target. But at the same time with Option 1, I see that b is appended into VAR. I suspect it is caused by := assignment in the target, but I couldn't find anything specific about that.
VAR = a
all: VAR += b
all: foo
# Option 1. with this line output is "a b z"
# foo: VAR += z
# Option 2. with this line output is "a c"
# foo: VAR := $(VAR) c
#echo $(VAR)
The explanation is that expressions with := assignments in target specific variables are evaluated by Make right at the time of reading the makefile and not when executing recipes for targets.
This seems to be not explained at all in the corresponding chapter of Make manual

Variable based on active makefile target (outside rule)

I've got a build configuration that looks something like this:
build-for-x: X := yes
build-for-x: all
build-for-y: Y := yes
build-for-y: all
SRC :=
all: # ... some targets which use SRC eventually
ifeq ($(X),yes)
SRC += foo_x.c
ifeq ($(Y),yes)
SRC += foo_y.c
ifeq ($(X),yes)
SRC += bar_x.c
ifeq ($(Y),yes)
SRC += bar_y.c
This is obviously highly simplified. What I'm actually doing is building the same codebase for two different embedded platforms, with many different modularized sections (foo and bar here) and several variables for source, include, tests, etc.
The above doesn't work, because X or Y are only set within the targets which build-for-x/build-for-y have as prerequisites. The code within is evaluated beforehand, when neither variable is set.
Is there a good way to handle situations like this? What's a sane way I might restructure my build configuration to:
Preserve the modularity ( are separate files)
Allow one to run make build-for-x/make build-for-y to build the separate implementations
I want to avoid making look something like:
build-for-x: SRC += foo_x.c
build-for-y: SRC += foo_y.c
unless I absolutely have to, since this forces me to have a dependency on a particular target. I would much rather keep all the target-dependent assignments at the top level.
How about this:
build-for-x: SRC := SRC_X
build-for-x: all
build-for-y: SRC := SRC_Y
build-for-y: all
SRC_X += foo.x_c
SRC_Y += foo.y_c
SRC_X += bar.x_c
SRC_Y += bar.y_c

how to parse parameter value passed to make file

I have a makefile which takes a TYPE parameter and runs a test file using that name. Otherwise it takes all the test files.
ifneq (,$(TYPE))
TEST_SRCS := $(wildcard test/$(TYPE)Test.cpp)
TEST_SRCS := $(wildcard test/*Test.cpp)
echo $(TEST_SRCS)
This works fine If I execute like,
make TYPE=Add
But Now I want to give more than one value to TYPE So that it should take both AddTest.cpp and SubtractTest.cpp
make TYPE=Add,Subtract
I have tried $(foreach var,$(TYPE), TEST_FILES += var)
Make isn't good at this kind of manipulation, but you can break a comma-separated list into a space-separated list like this:
TYPE_LIST = $(subst $(COMMA), ,$(TYPE))
Then you can apply your wildcard logic like this:
FILE_LIST = $(patsubst %,test/%Test.cpp,$(TYPE_LIST))
TEST_SRCS := $(wildcard $(FILE_LIST))