I want to recompile version.c whenever an other c-file has changed. So i tried to touch the c-file whenever an other c-file has changed. The Problem is that make doesn't recognize the change when it is allready doing the c-compiling. I think the reason is that it has already updated all dependencies. Is there a way to break the chains?
For example:
$(TARGET): $(OBJECTFILES) $(TARGET).a
$(OBJECTDIR)/%.o: %.c | $(OBJECTDIR)
$(if $(filter $(VERSION_BUILD),0),$(shell touch $(PROJECT_ROOT_PFAD)/$(VERSION_FILE)))
#When VERSION_FILE then VERSION_BUILD is set to 1
$(CC).....
So i want make to recognize the updated file immediately.
I want to recompile version.c whenever an other c-file has changed.
So, you must declare that the result of the compilation of version.c depends on the other C source files. The following computes the list of the other C source files and assigns it to a make variable:
OTHER_C_SOURCES := $(filter-out version.c,$(wildcard *.c))
The result of the compilation of version.c is version.o. The rule you need is thus:
version.o: version.c $(OTHER_C_SOURCES)
$(CC) -c $(CFLAGS) $< -o $#
That's it. It says: if version.c or any of the other source files change, rebuild version.o by executing:
$(CC) -c $(CFLAGS) version.c -o version.o
($< expands as the first pre-requisite - version.c - and $# as the target - version.o).
Note: the solution you are using is very far from the normal make strategy. You should probably reconsider all this and base your Makefile on the classical target: pre-requisites dependency graph.
The youltion was to add version.c at the very last to OBJECTFILES because it all depends of the order.
fileA.c
version.c
fileB.c
If touched version.c when it compiles fileA.c then version.c was recompile but not when version.c was touch when fileB.c was compiled because version.c was allready checked. So the solution is:
fileA.c
fileB.c
...
version.c
Related
Just to review the terminology, this is the structure of a makefile 'rule':
target: dependencies ...
commands
...
This is the makefile I've written:
CC = mpicc
SHAREDLIB = libfmd.so
CFLAGS = -fPIC -Wall -Wno-unused-result -O3 -fopenmp
LFLAGS = -lm -fopenmp -lgsl -lgslcblas
OBJS = $(patsubst %.c,%.o,$(wildcard *.c))
.PHONY: all shared clean
all: shared
shared: $(SHAREDLIB)
$(SHAREDLIB): depend.mk $(OBJS)
$(CC) $(OBJS) -shared -o $# $(LFLAGS)
depend.mk: *.c *.h
$(CC) -MM *.c > depend.mk
-include depend.mk
clean:
rm -f *.o libfmd.so depend.mk
When the folder is clean, and I enter make clean, the following lines are shown:
mpicc -MM *.c > depend.mk
rm -f *.o libfmd.so depend.mk
It seems to me that -include depend.mk in addition to including depend.mk, executes the rule that depend.mk is its target. I'd like to stop this behavior.
You are correct. See How Makefiles are Remade in the documentation.
There is no way to prevent this behavior: if there's a rule that creates an included makefile, make will always rebuild it if it's out of date, then re-invoke itself to read the latest version.
The question is, why do you want to avoid it? Maybe if you explained the behavior you are actually looking for at a higher level we could help. As you have it here it's possible for .o files to be created without any depend.mk file created, then a compile fails, you modify a header file to fix it, but since the depend.mk file doesn't exist when you re-run make the source files are not rebuilt properly.
If you want to get accurate handling of C/C++ dependencies with GCC you might take a look at Auto-Dependency Generation.
depend.mk: *.c *.h
$(CC) -MM *.c > depend.mk
FYI, this is wrong, as make doesn't support shell wildcards in a rule string. Although on a recipe line that could work as it gets expanded by the shell itself.
I'd like to stop this behavior
depend.mk is a prerequisite of the default target, so it is a target anyway.
Also, preprocessing into depend.mk is slow for large projects, so it totally makes sense either to switch to manually written dependencies, or use a recommended way to generate them, as #MadScientist suggested.
Hello I have a shared library libnsd.so (made up of nsd.c,nsd.h,nd.c,nd.h) linked to main file.
My question is how to write the makefile so that it recompiles only those source files that have been changed.
I have read some topics about this but got somewhat confused, I'm a beginner programmer.
My makefile code so far:
CC=gcc
all : lib alll
alll : main.c
$(CC) main.c -o main -L. libnsd.so
lib : nsd.c nsd.h nd.c nd.h
$(CC) -c -fPIC nsd.c -o nsd.o
$(CC) -c -fPIC nd.c -o nd.o
$(CC) -shared -Wl,-soname,libnsd.so -o libnsd.so nsd.o nd.o
clean:
rm main libnsd.so nd.o nsd.o
Makefiles have the concept of build targets. The build targets are, really, all the intermediate as well as the final files and, by the way they are written, they can be made to use dependencies.
A sample solution for your makefile:
CC=gcc
all: main
main: main.c libnsd.so
$(CC) main.c -o main -L. libnsd.so
libnsd.so: nsd.o nd.o
$(CC) -shared -Wl,-soname,libnsd.so -o libnsd.so $#
%.o: %.c nsd.h nd.h
$(CC) -c -fPIC $< -o $#
A few things to note:
You should properly correct my dependencies on the object file creation (since I consider that each of the C files depends on both of the headers).
You may wish to note the wildcard construction I have used...
If there was nothing special with some of these commands I could have left default commands work. Do note that I have used $< for the first dependency and $# for the output in the wildcard rule.
I haven't copied the clean rule, since it was written correctly in the question itself.
Each of the targets (besides the "phony" target all) creates a file with the same name: The target libnsd.so creates a file with the name libnsd.so. The target main creates a file with the name main.
As a dependency of a target changes date so that the dependency is newer than the output, make will recreate the target, as well as other targets that depend on it. But if you have a target that is not mapped to any output file, that target is always called (in our code, the all target is always called but thankfully it has no commands and it depends only on actual files which may or may not need being recreated)
Do note that GNU Make doesn't need to have compiling in particular. The creation of an output file can happen by any means, and indeed I have seen a target create a .cpio.gz archive. But if that archive is older than any of the dependencies (the folder it would pack in) then it would be recreated, according to make.
I am having problems with this makefile. I want to each .cpp file get a dependency .hpp eg: a file main.cpp have a dependency main.hpp
The makefile works well, but when I modify main.hpp, Make is not rebuilding.
Can someone give me a hint. Thanks
objetivo=control
objetos=$(shell ls *.cpp | sed 's/cpp/o/')
optimizacion=-O2 -pipe
enlaces=-lncurses -lmenu -lpq -lform -lcdkw
CPP=g++ -std=c++11 -Wall
.PHONY: all clean debug rebuild
all: $(objetivo)
.cpp.o: $*.hpp
$(CPP) $(optimizacion) -c $<
debug: CPP += -g
debug: optimizacion=
debug: $(objetivo)
rebuild: clean all
$(objetivo): $(objetos)
$(CPP) -o $# $(enlaces) $(objetos)
clean:
-rm *.o $(objetivo)
Your solution is not right. Now the .o will be rebuilt whenever the .hpp file changes, but it won't be rebuilt when the .cpp file changes!
If you want to have two different prerequisites, you have to list them both:
%.o: %.cpp %.hpp
$(CPP) $(optimizacion) -c $<
Note that CPP is not the usual variable for a C++ compiler; the standard variable is CXX.
The reason your first attempt didn't work is that old-style suffix rules don't allow any prerequisites. See the manual for details.
I found a solution.
I replaced the rule .ccp.o to:
%.o: %.hpp %.cpp
$(CPP) $(optimizacion) -c $*.cpp
Now every time I modify the related hpp Make rebuild the matched .cpp
Thanks anyway
I am using make which calls g++ always re-compiles the code, even when I do not change the source code. That happens for all my projects, even for simple ones such as:
[code]
all: main.cpp
g++ -std=c++11 -c main.cpp
[/code]
I believe it should compare the date/time on source and object code. Could some help me with this, I am running using GNU toolchain on Ubuntu 12.04
THX
Edit: sorry guys, I do use Makefile, I edited my question accordingly.
Simplest Makefile
It was already pointed out that your Makefile is probably wrong. The 'all' target is indeed always built (although it may result in a no-op if it has no commands and all dependencies are already satisfied). All you need in your makefile is this:
all: main
Object files
If you expect to have more source file in your build, you should consider creating intermediate object files:
all: main
main: main.o
Tweak the build
Make will automatically find the main.ccp file and turn it into main which is required per the directive above. You can use special make variables to further tweak the compilation, e.g. for debug information inclusion and for warning configuration:
CXXFLAGS = -g -Wall -Werror
all: main
main: main.o
Nitpicking
If you insist on building up the compile rule yourself, you can do it like this:
%.o: %.hpp
$(CXX) $(CPPFLAGS) $(CXXFLAGS) -o $# -c $<
CXX: C++ compiler
CPPFLAGS: C preprocessor flags
CXXFLAGS: C++ compiler flags
$#: Target
$<: First dependency
If you don't want to use the standard variables nor pattern matching, you can build up the whole makefile explicitly:
all: main
main: main.o
gcc -o $# $^
main.o: main.c
gcc -g -Wall -Werror -o $# -c $<
$^: Use that one if you want to include all dependencies, for example if you have multiple *.o files to build one binary.
Note: It is a bad idea to write the file names directly into the command as you might forget to update them later.
all: main.cpp
g++ -std=c++11 -c main.cpp
This seems wrong. Why does the rule for all has main.cpp as its target? Shouldn't it be something.exe or something.o? Say
all: main.exe
main.exe: main.cpp
g++ -std=c++11 main.cpp -o main.exe
clean:
del main.exe
Targets are output files and cpp files are source code which should be input to the make system.
g++ would have to "recompile" in general (what happens if you change the header but not main.cpp?)
If you are concerned about long build times, you should use something like Make (which is designed specifically to avoid recompiling when the source hasn't changed)
The compiler will always compile the code. If you want to do conditional compilation (based on file times etc) you will need to use a make system such as Make, CMake, Ant, etc. For the simplest you can set up a small "Makefile" in the directory and use the command "make" to build.
Simple Makefile for compiling "myapp.exe" from "main.cpp", "file1.cpp" and "file2.cpp"
myapp.exe: main.o file1.o file2.o
g++ -o myapp.exe main.o file1.o file2.o
(make knows to use .cpp files to build .o files)
But if you also have header files, then you will need to build dependency chains, for which you may want to look into something more sophisticated like automake, cmake, ant, etc.
---- EDIT ----
Based on your updated post, the problem is that you aren't specifying a target, so Make has to assume it needs to recompile. See my example in the above answer.
I am new to make files and I put this together with a bit of trial & error. This code is used to compile my c++ program.
My main.cpp file in the same folder as the makefile. I have a lib/ folder that contains the headers main depends on.
The following makefile results in a correct and complete compilation of my code. But I was expecting that I would find *.o objects left behind. (Note that I've tried to make both with and without the "clean" rule, and I get the same results both times.)
#
# Makefile
#
CXX = g++
CCFLAGS = -O3 -I/sw/include -L/sw/lib
## /sw/include and /sw/lib contain dependencies for files in my lib/
LDFLAGS = -lpng
OPTS = $(CCFLAGS) $(LDFLAGS)
SOURCES = $(wildcard lib/*.cpp) main.cpp
OBJECTS = $(SOURCES: .cpp = .o)
TARGET = spirals
$(TARGET): $(OBJECTS)
$(CXX) $(OPTS) $^ -o $#
.PHONY: depend
depend:
g++ -MM $(SOURCES) > depend
## generate dependencies list
include depend
.PHONY: clean
clean:
rm -f *.o lib/*.o $(TARGET)
Also, in case it matters, I'm on MacOSX and my program is designed in xcode. (I know that xcode has its own build flow, but I'm designing a command-line program for a linux system and I'd like to test compilation & linking in a bash environment instead of only going through xcode.)
Questions:
Am I correct to expect makefiles to produce *.o files that stick around once the main target has been created?
If so, why doesn't my makefile do this?
If you observe what command your $(TARGET) rule causes to be run:
g++ -O3 -I/sw/include -L/sw/lib -lpng lib/bar.cpp lib/foo.cpp main.cpp -o spirals
you'll see that $(OBJECTS) in fact contains *.cpp files, and there are no *.o files sticking around because you haven't asked for any.
The problem is here:
OBJECTS = $(SOURCES:.cpp=.o)
In your GNU makefile as written, this substitution reference is written with excess spaces, so never matches anything and $(OBJECTS) ends up the same as $(SOURCES). Rewrite it as above and it'll do what you expect.
(Other notes: -lpng needs to go at the end of the link command to work in general, so you should introduce another make variable (traditionally called $(LDLIBS)) so as to arrange that. Especially as someone new to makefiles, you would do better to spell out your dependencies explicitly rather than playing games with $(wildcard) and a computed $(OBJECTS). -I options are needed during compilation while -L options are used during linking, so it would be good to arrange separate $(CXXFLAGS)/$(LDFLAGS) variables used in separate rules so they are only added when required.)