counter not incrementing for RAM with built-in counter - vhdl

Question

I am new to vhdl and trying create a RAM in which I first write data then I read that data. The task is supposed to be created using a FSM. I have created the behavioral code as follows along with its test bench but the counters are not incrementing and I dont get it.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sorting is
port (
clk : in std_logic;
en : in std_logic;
data_in : in std_logic_vector(23 downto 0);
data_out : out std_logic_vector(23 downto 0));
end entity;
architecture bhv of sorting is
type internal_ram is array(1 downto 0) of std_logic_vector(23 downto 0);
signal int_ram_in : internal_ram;
signal int_ram_out : internal_ram;
type state_type is (s0, s1, s2); --stages is fsm
signal state, nxt_state : state_type;
signal cntr_in : integer range 0 to 3;--unsigned(1 downto 0); --read counter
signal cntr_out : integer range 0 to 3;-- unsigned(1 downto 0); --write counter
begin
-- fsm_loop : process(clk)
-- begin
-- if rising_edge(clk) then
-- if (en = '1') then
-- state <= s0;
-- else
-- state <= nxt_state;
-- end if;
-- end if;
-- end process;
comp_loop : process(clk, state, en, data_in)
begin
if rising_edge(clk) then
case(state) is
when s0 =>
if (en = '1') then
cntr_in <= 0;
cntr_out<= 0;
else
nxt_state <= s1;
end if;
when s1 => --writing in internal_ram
if (cntr_in = 3) then
cntr_in <= 0;--(others => '0');
nxt_state <= s2;
else
cntr_in <= cntr_in + 1;
int_ram_in(cntr_in) <= data_in;
end if;
when s2 => --using data_in
if (cntr_out = 3) then
cntr_out <= 0;--(others => '0');
nxt_state<= s0;
else
cntr_out <= cntr_out + 1;
data_out <= int_ram_in(cntr_out);
end if;
end case;
end if;
end process;
end bhv;
The test bench used is:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sorting_tb is
end entity sorting_tb;
architecture tb of sorting_tb is
component sorting
port (
clk : in std_logic;
en : in std_logic;
data_in : in std_logic_vector(23 downto 0);
data_out : out std_logic_vector(23 downto 0)
);
end component;
signal clk : std_logic := '0';
signal en : std_logic := '1';
signal data_in : std_logic_vector(23 downto 0);
signal data_out : std_logic_vector(23 downto 0);
begin
mapping: sorting port map(
clk => clk,
en => en,
data_in => data_in,
data_out => data_out);
clock: process
begin
clk <= '1'; wait for 10 ns;--50MHz clk
clk <= '0'; wait for 10 ns;
end process;
stimuli: process
begin
--1st run
wait for 10ns;
en <= '0';
data_in <= "111100001111000011110000";
wait for 20ns;
data_in <= "111100001111000011110001";
wait for 20ns;
data_in <= "111100001111000011110010";
wait for 20ns;
data_in <= "111100001111000011110011";
-- en <= '1';
wait for 200ns;
en <= '1';
--2nd run
wait for 20ns;
en <= '0';
data_in <= "001100001111000011110000";
wait for 20ns;
data_in <= "011100001111000011110001";
wait for 20ns;
data_in <= "101100001111000011110010";
wait for 20ns;
data_in <= "111100001111000011110011";
-- en <= '1';
wait for 200ns;
en <= '1';
end process;
end tb;
And the simulation that I get is this: