I'm new to Linux, so for my undergraduate project, I am working on Ubuntu and I have been trying to configure Freeswitch...almost having a breakthrough. Then finally, to use make && make install, it brought:
"makefile:1: *** target pattern contains no '%'. Stop."
Please, what should I do
Well, it would help greatly if you provided the content of your makefile at line 1 (where the error is reported to be, by makefile:1:). Without that we can only guess.
But basically what that message means is that you have used static pattern rule syntax, but your target pattern(s) don't contain any pattern token (%). What this usually means is you have a "stray" colon in your rule that you didn't expect or want. Without seeing your makefile rules we can't say more than that.
Also very useful is the GNU make manual section Errors Generated by Make which should give you a description of the error.
Related
Here is the make file that I am running,
.PHONY: build
build: pre_build_script $(OUTPUTDIR)/%.cpp
$(OUTPUTDIR)/%.cpp: $(INTXTDIR)/%.txt
python.exe $(SOMEDIR)/somepythonscript.py $(INTXTDIR) $(OUTPUTDIR)
.PHONY: pre_build_script
pre_build_script:
pythonscript.exe $(PREBUILDDIR)
This is the output that I get:
$ make build
pythonscript.exe $(SAMPLEDIR)
make: *** No rule to make target '../obj/CPP/%.cpp', needed by 'build'. Stop.
Looks like I'm missing on some sytanx as I get this error inspite of declaring the target dependency. Any suggestions?
This means make cannot find a file named $(OUTPUTDIR)/%.cpp, a prerequisite for the first rule.
You cannot use % as a wildcard anywhere in a rules like this:
build: pre_build_script $(OUTPUTDIR)/%.cpp
it needs to be a part of pattern rule or a static pattern rule.
You can use $(wildcard $(OUTPUTDIR)/*.cpp) to get a complete list of files, but it's an anti-pattern (pun intended). You are supposed to either exactly know what files are used in what rules, or (know it even better and) create a generic pattern rule.
The second pattern rule (one using somepythonscript.py) is supposed to work on a single source-target file pair, $(INTXTDIR)/%.txt -> $(OUTPUTDIR)/%.cpp. The command seems to process all the files in the directory, which is not incremental: it will redo all the work even if only one file was updated.
Why does my Makefile not work?
makefile:
app-reset:
bin/console avanzu:admin:fetch-vendor
make app-reset is returning:
makefile:3: *** target pattern contains no `%'. Stop.
As explained in https://www.gnu.org/software/make/manual/make.html#Recipe-Syntax, every line in your build recipe must start with a tab character. If you use anything else (such as a sequence of spaces), you get confusing errors.
Usually this manifests as Makefile:42: *** missing separator. Stop. but in your case the colons (:) in your command confused make into thinking you were trying to define a pattern rule.
In any case, the solution is to use a tab character instead. (Or, if you are using GNU make, set .RECIPEPREFIX.)
Can you try this?
sudo apt-get install lib32ncurses5 lib32z1
I meet same problem in 18.04, but I pass the make after install lib32ncurses5 lib32z1.
I want to have a generic Makefile that takes any target name and for that target name, checks to see if certain sources exist and then executes some commands. So for example I want to be able to enter:
make mytarget
then make should check to see if mytarget.src1 and mytarget.src2 exist, and if so execute some commands.
I have the following makefile:
%:
$(MYCOMMANDS) $*.scr1 $*.scr2
the only problem with this is that it doesn't check to see if $.scr1 and $.scr2 exist before running $(MYCOMMANDS). This is understandable because I haven't specified any dependencies. However when I try:
%: $*.src1 $*.src2
$(MYCOMMANDS) $*.scr1 $*.scr2
it now doesn't ever run $(MYCOMMAND) and says no rule to make the specified target.
Can someone please explain why in my second code make cannot find the target? Also, how can I achieve the behavior that I want?
The correct way to write a pattern rule is to use the pattern (%) in both the target and the prerequisites:
%: %.src1 %.src2
$(MYCOMMANDS) $^
See Pattern Rules in the GNU make manual. Also see Automatic Variables. By the way, the third paragraph in the second link will explain why your second attempt, using $* in the prerequisites, cannot work.
I was able to get the behavior I want using the MAKECMDGOALS variable. So:
$(MAKECMDGOALS): $(MAKECMDGOALS).src1 $(MAKECMDGOALS).src2
$(MYCOMMANDS) $(MAKECMDGOALS).scr1 $(MAKECMDGOALS).scr2
does what I am looking for. It checks to make sure .src1 and .src2 exist. If they don't make will report an error and if they do it will run $(MYCOMMANDS).
I am trying to build mysql-workbench from source (for a 32 bit Fedora 22).
After many attempts and fixes, I got the following error:
plugins/migration/CMakeFiles/wbcopytables-bin.dir/build.make:163: *** target pattern contains no '%'. Stop.
Line build.make:163 is
plugins/migration/wbcopytables-bin: /bin/sh:\ /root/linux-res-6.3/usr/bin/iodbc-config:\ No\ such\ file\ or\ directory
Do you see any typo, with respect to Make and its syntax of Static Pattern Rules? Or am I on a complete wrong track?
Also, is there a way to check corrections of line 163 without to build the entire .rpm (which takes almost 1h)?
m.
As there is not enough information given in the question, this answer is given on the grounds that it is easy to reproduce the error message in a way that appears to emulate what line 168 has in it.
Given a Makefile that contains a construct something this:
this: that: somethingelse:
echo the stuff
The error message in the question results:
$ make this
Makefile:1: *** target pattern contains no `%'. Stop
And further, since the line 168:
plugins/migration/wbcopytables-bin: /bin/sh:\ /root/linux-res-6.3/usr/bin/iodbc-config:\ No\ such\ file\ or\ directory
looks an awful lot like:
this: that: somethingelse:
build.make rather seems to have been generated by some script that encountered an error and output:
/bin/sh: /root/linux-res-6.3/usr/bin/iodbc-config: No such file or directory
It would further appear that said script probably for some reason redirected stderr onto stdout or whatever file descriptor was being used to generate build.make, with the result being that the generated file was so damaged as to produce this error.
Of course, all this presupposes much and the question provides far too little contextual information, but certainly this explanation seems plausible.
In a real Makefile, one would correct the situation by removing the colons from all but the final target name, but the OP's file is apparently compromised since it is most improbable that the error message was ever intended to be a target name.
Let me illustrate it with an example.
mkdir test
cd test
touch target
make target
This will result in: make: Nothing to be done for 'target'.
So make tells me there is nothing to do. This is because make did not find a rule to make target, but because the target already exists make tells me there is nothing to do.
Now, I don't want that. I want make to give me an error when it cannot find a rule for target, even though the target already exists.
I have tried the following:
echo '.DEFAULT:
echo make: *** No rule to make target `$#'. Stop.
false'> Makefile
But this does not stop the make when making multiple targets.
The problem is, that make assumes the target name is also a file which will be build by the given commands.
But sometimes this is not true (e.g. think of "clean").
To tell make that some targets don't build this file, you need to make them "phony". Put the following line into your Makefile:
.PHONY: target
If you think about it, you would end up with a chicken-and-egg situation (or infinite regress). Suppose you managed to have a rule that said 'You must have a rule to create target before it is legitimate', then you'd have a rule that says 'target depends on X' for some other file X. That's written:
target: X
command to build target from X
But then you'd be back to the starting point: you'd also want a rule to create X. How can you do that? You might have a rule that depends on nothing and magically creates the file X when it is needed:
X:
command to build X from nothing
Without a rule like that, you have an infinite regress.
So, make is designed to ensure that files exist and are up to date. If a file exists and there are no rules - implicit or explicit - to specify how it is made, then the file is up to date. What you are seeking to do is not possible.
Actually this sounds like a perfectly reasonable (if misguided ;-)) request. You will have to explicitly list every source file with a rule with an empty recipe though.
Here you go:
Makefile: ;
.PHONY: dodgy
dodgy%: dodgy; $(error You must provide a rule for $*)
%: dodgy% ;
The proof of the pudding:
$ rm aa
$ make aa
Makefile:4: *** You must provide a rule for aa. Stop.
$ touch aa
$ make aa
Makefile:4: *** You must provide a rule for aa. Stop.
Note that the line Makefile: ; is necessary. After all, the first thing make tries to do is rebuild the Makefile.
Note also that the catch-all pattern rule is non-terminal. This can be a massive performance hit. As the manual says about match anything rules "They are very useful, but it can take a lot of time for make to think about them."