VHDL Concurrent Array Assignment - Memory Structure gets wiped - vhdl

Question

I've been wrestling with a rather large project and I've come to an impasse, the following code simulates and works as expected except that it reassigns all memory addresses to UU upon a signal assignment. The code describe a fully descending stack with integrated stack pointer. I'm trying to avoid process statements for timing purposes and I would really like the memory block to remain a signal array (and not a variable array) for debugging purposes.
The selected address data must be present upon the rising clock edge (immediately) and must be completely stored and ready for re-reading no later than the falling edge of the same clock signal.
Maybe I've just been staring at my description for too long, but I don't understand why it's reassigning every value to UU when I write to a single address. There's definitely a VHDL rule I'm breaking here. I would like both an asynchronous reset to clear the entire array, as well as a synchronous read/write. If advisable, I would like to eventually remove the clock dependency altogether.
Here's the relevant code block:
-- Fully Descending Stack with integrated Stack Pointer --
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY STACK IS
GENERIC(
BIT_WIDTH : INTEGER := 10;
BIT_DEPTH : INTEGER := 5
);
PORT(
CLK : IN STD_LOGIC;
CE : IN STD_LOGIC;
RESET : IN STD_LOGIC;
LOAD : IN STD_LOGIC;
PUSH : IN STD_LOGIC;
POINTER_WRITE_ADDRESS : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0);
STACK_DATA_IN : IN std_logic_vector(BIT_WIDTH - 1 DOWNTO 0);
-- OUTPUT SIGNALS --
POINTER_ADDRESS : OUT STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0) := (OTHERS => '0');
STACK_DATA_OUT : OUT std_logic_vector(BIT_WIDTH - 1 DOWNTO 0) := (OTHERS => '0');
STACK_FULL : OUT STD_LOGIC := '0';
STACK_EMPTY : OUT STD_LOGIC := '1'
);
END STACK;
ARCHITECTURE Behavioral OF STACK IS
CONSTANT STACK_DEPTH : INTEGER := (2**BIT_DEPTH) - 1;
SUBTYPE WORD_SIZE IS std_logic_vector(BIT_WIDTH - 1 DOWNTO 0);
TYPE MEMORY IS ARRAY (STACK_DEPTH DOWNTO 0) OF WORD_SIZE;
SIGNAL STACK_MEMORY : MEMORY := (OTHERS => (OTHERS => '0'));
SIGNAL STACK_POINTER : INTEGER := STACK_DEPTH;
BEGIN
STACK_MEMORY <= (OTHERS => (OTHERS => '0')) WHEN RESET = '1' ELSE
(to_integer(unsigned(POINTER_WRITE_ADDRESS)) => STACK_DATA_IN) WHEN LOAD = '1' AND rising_edge(CLK) ELSE
( STACK_POINTER => STACK_DATA_IN) WHEN (PUSH = '1' AND CE = '1' AND NOT (STACK_POINTER = 0)) AND rising_edge(CLK);
STACK_POINTER <= (STACK_POINTER + 1) WHEN PUSH = '0' AND CE = '1'AND NOT(STACK_POINTER = STACK_DEPTH) AND rising_edge(CLK)ELSE
(STACK_POINTER - 1) WHEN PUSH='1' AND CE = '1' AND NOT (STACK_POINTER = 0) AND rising_edge(CLK);
STACK_EMPTY <= '1' WHEN STACK_POINTER = STACK_DEPTH else '0';
STACK_FULL <= '1' WHEN STACK_POINTER = 0 else '0';
STACK_DATA_OUT <= STACK_MEMORY(STACK_POINTER+1) WHEN CE = '1' AND PUSH='0' AND (NOT(STACK_POINTER = STACK_DEPTH)) ELSE
STACK_DATA_IN WHEN LOAD='1' or (CE = '1' AND PUSH='1' AND
NOT(STACK_POINTER = 0))ELSE
(OTHERS => '0') WHEN (STACK_POINTER = STACK_DEPTH);
POINTER_ADDRESS <= std_logic_vector(to_unsigned(STACK_POINTER,
POINTER_ADDRESS'length));
END Behavioral;
------------------------------EDIT--------------------------------
Okay, I've taken a look at some reference material and rewritten my code as follows:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY STACK IS
GENERIC(
-- DATA STORAGE GENERICS --
BIT_WIDTH : INTEGER := 10;
BIT_DEPTH : INTEGER := 8
);
PORT(
-- NON-SPECIFIC INPUT SIGNALS --
CLK : IN STD_LOGIC;
CE : IN STD_LOGIC;
RESET : IN STD_LOGIC;
-- STACK OPERATION INPUT SIGNALS --
LOAD : IN STD_LOGIC;
PUSH : IN STD_LOGIC;
POINTER_WRITE_ADDRESS : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0);
STACK_DATA_IN : IN std_logic_vector(BIT_WIDTH - 1 DOWNTO 0);
-- OUTPUT SIGNALS --
POINTER_ADDRESS : OUT STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0) := (OTHERS => '0');
STACK_DATA_OUT : OUT std_logic_vector(BIT_WIDTH - 1 DOWNTO 0) := (OTHERS => '0');
STACK_FULL : OUT STD_LOGIC := '0';
STACK_EMPTY : OUT STD_LOGIC := '1'
);
END STACK;
ARCHITECTURE Behavioral OF STACK IS
CONSTANT STACK_TOP : INTEGER := (2**BIT_DEPTH) - 1;
SUBTYPE WORD_SIZE IS STD_LOGIC_VECTOR(BIT_WIDTH - 1 DOWNTO 0);
TYPE MEMORY IS ARRAY (STACK_TOP DOWNTO 0) OF WORD_SIZE;
SIGNAL STACK_MEMORY : MEMORY := (OTHERS => (OTHERS => '0'));
SIGNAL STACK_POINTER : INTEGER := STACK_TOP;
SIGNAL STACK_POINTER_INPUT : INTEGER := 0;
BEGIN
STACK_POINTER_INPUT <= to_integer(unsigned(POINTER_WRITE_ADDRESS));
POINTER_ADDRESS <= std_logic_vector(to_unsigned(STACK_POINTER, POINTER_ADDRESS'length));
STACK_POINTER_CONTROL : PROCESS(CLK)
BEGIN
IF (Rising_Edge(CLK)) THEN
IF (RESET = '1') THEN
STACK_POINTER <= STACK_TOP;
ELSIF (LOAD = '1') THEN
STACK_POINTER <= STACK_POINTER_INPUT;
ELSIF (CE = '1' AND PUSH = '0' AND STACK_POINTER < STACK_TOP) THEN
STACK_POINTER <= STACK_POINTER + 1;
ELSIF (CE = '1' AND PUSH = '1' AND STACK_POINTER > 0) THEN
STACK_POINTER <= STACK_POINTER - 1;
END IF;
END IF;
END PROCESS STACK_POINTER_CONTROL;
BLOCK_MEMORY_CONTROL : PROCESS(CLK)
BEGIN
IF (Rising_Edge(CLK)) THEN
IF (RESET = '1') THEN
STACK_MEMORY <= (OTHERS => (OTHERS => '0'));
-- POP | Erase data from popped address --
ELSIF (CE = '1' AND PUSH = '0') THEN
STACK_MEMORY(STACK_POINTER) <= (OTHERS => '0');
-- PUSH | Write data to stack pointer --
ELSIF (CE = '1' AND PUSH = '1') THEN
STACK_MEMORY(STACK_POINTER) <= STACK_DATA_IN;
END IF;
END IF;
END PROCESS BLOCK_MEMORY_CONTROL;
STACK_DATA_OUT <= (OTHERS => '0') WHEN RESET = '1'
ELSE STACK_DATA_IN WHEN STACK_POINTER = 255
ELSE STACK_MEMORY(STACK_POINTER + 1);
STACK_EMPTY <= '1' WHEN STACK_POINTER = STACK_TOP else '0';
STACK_FULL <= '1' WHEN STACK_POINTER = 0 else '0';
END Behavioral;
It now seems to operate correctly in all simulation tests, but I'm worried about timing conflicts between states. Is there a better way to improve upon this design?