I am doing some simple tests to evaluate how clock speed increases in a digital circuit when pipelining.
I pipeline an 10to1 mux using 2 5to1 and 1 2to1. I get some clock speed increase from the fpga synthesizer (altera). Then I add one more stage, replacing the he 5to1 muxes with 2to1 and 3to1 and appropriate registers. In the latter case the clock speed drops. I don't get why adding registers and pipeline stages would drop the clock speed..any explanations?
The minimal logic gate in most FPGAs is a lookup table (LUT) They came with 3 to 6 inputs. Altera's ALMs are configurable in many ways. In either way, if a multiplexer size is lower then the equivalent LUT size, there will be no further Fmax improvement.
You could describe all multiplexer sizes as trees of 2:1 multiplexers. Synthesis will optimize the resulting equations and map them to LUT structures and configurations of your FPGA device.
You can further use a user-defined rising_edge function to create a variable pipelining:
function registered(signal Clock : std_logic; constant IsRegistered : boolean) return boolean is
begin
if IsRegistered then
return rising_edge(Clock);
end if
return TRUE;
end function;
(Source: PoC-Library - components package)
This function allows you to selectivly enable and disable pipeline stages.
Related
I have designed an algorithm-SHA3 algorithm in 2 ways - combinational
and sequential.
The sequential design that is with clock when synthesized giving design summary as
Minimum clock period 1.275 ns and Maximum frequency 784.129 MHz.
While the combinational one which is designed without clock and has been put between input and output registers is giving synthesis report as
Minimum clock period 1701.691 ns and Maximum frequency 0.588 MHz.
so i want to ask is it correct that combinational will have lesser frequency than sequential?
As far as theory is concerned combinational design should be faster than sequential. But the simulation results I m getting for sequential is after 30 clock cycles where as combinational there is no delay in the output as there is no clock. In this way combinational is faster as we are getting instant output but why frequency of operation of combinational one is lesser than sequential one. Why this design is slow can any one explain please?
The design has been simulated in Xilinx ISE
Now I have applied pipe-lining to the combinational logic by inserting the registers in between the 5 main blocks which are doing the computation. And these registers are controlled by clock so now this pipelined design is giving design summary as
clock period 1.575 ns and freq 634.924 MHz
Min period 1.718 ns and freq 581.937.
So now this 1.575 ns is the delay between any of the 2 registers , its not the propagation delay of entire algorithm so how can i calculate propagation delay of entire pipelined algorithm.
What you are seeing is pipelining and its performance benefits. The combinational circuit will cause each input to go through the propagation delays of the entire algorithm, which will take at up to 1701.691ns on the FPGA you are working with, because the slowest critical path in the combinational circuitry needed to calculate the result will take up to that long. Your simulator is not telling you everything, since a behavioral simulation will not show gate propagation delays. You'll just see the instant calculation of your combinational function in your simulation.
In the sequential design, you have multiple smaller steps, the slowest of which takes 1.275ns in the worst case. Each of those steps might be easier to place-and-route efficiently, meaning that you get overall better performance because of the improved routing of each step. However, you will need to wait 30 cycles for a result, simply because the steps are part of a synchronous pipeline. With the correct design, you could improve this and get one output per clock cycle, with a 30-cycle delay, by having a full pipeline and passing data through it at every clock cycle.
Using a Stratix II FPGA is it possible to generate a clock output with a frequency much higher than 200MHz? (Up to 400 or 500MHz) If so how can I achieve this?
I used a PLL to generate 200MHz out of a 100MHz clock and this seems to work. But turning the PLL to 250MHz will make the TimeQuest Timing Analyzer reporting a negative setup slack for the PLL in the slow model. So I wonder if there is a better way to generate such high frequency clock outputs...
how can i access four elements from a 2d array or array of array in one process at the same time?
in this sample, i am trying to access intg1 at the same time, the synthesis is taking for ever.
type img_whole is array (78 downto 0, 130 downto 0) of std_logic_VECTOR(7 downto 0);
signal img1: img_whole;
signal i1_1: integer range 0 to 79:=0;
signal j1_1:integer range 0 to 131:=0;
type intg is array (78 downto 0, 130 downto 0) of integer range 0 to 1751998;--no double??
signal intg1 : intg;
integral :process (clka,finished,finished1)
variable tempo: integer range 0 to 1751998;
begin
if clka'event and clka = '1' then
if finished="1" and finished1="0" then
if i1_1 < 78 and j1_1 <130 then
j1_1<=j1_1+1;
elsif j1_1=130 and i1_1<78 then
j1_1<=0 ;
i1_1<=i1_1+1;
elsif j1_1<130 and i1_1=78 then
j1_1<=j1_1+1;
elsif j1_1=130 and i1_1=78 then
finished1<="1";
end if;
tempo:= to_integer(unsigned('0' & img1(i1_1,j1_1)));
if i1_1-1>=0 then
tempo:=intg1(i1_1-1,j1_1)+tempo;
end if;
if j1_1-1>=0 then
tempo:=intg1(i1_1,j1_1-1)+tempo;
end if;
if i1_1-1>=0 and j1_1-1>=0 then
tempo:=tempo-intg1(i1_1-1,j1_1-1);
end if;
intg1(i1_1,j1_1)<=tempo;
end if;
end if;
end process;
i am trying to access intg1 at the same time, the synthesis is taking for ever.
this code is for getting an integral image, out of a 2d array.
There are both functional and synthesis issues in the code.
Functional issues:
finished1 is only driven to '1' in the process, but never to '0', so if the initial value is '0' then the operation in the process can only be done once after power up, since the finished1 value of '1' will then inhibit further updates due to the process enable condition.
i1_1 and j1_1 are signals that are driven in the start of the process, and then used later in the process, but since signals, the value assigned with <= is not available until next process evaluation. Is that intentional?
Use a simulator to ensure correct functionality, which can be done before synthesis.
Synthesis issues:
intg1 is a table with at least 79 * 131 > 10 K entries, each of log2(1751999) <= 18 bits, thus a pretty large table. The design requires asynchronous lookup in the table, since there is no extra cycle (clock edge) available from a new value of index e.g. i1_1 and until the output of the process is generated based on the table lookup. An asynchronous lookup in a large table requires a huge mux network, which is probably the reason for the long synthesis time. And this lookup is even done multiple times based on different index values.
Minor: finished, and finished1 are not needed in the sensitivity list of the process, since this is a process clocked by the clka.
The above list of issues may not be complete.
To fix the table lookup problem (first synthesis issue), make a pipe-lined design with cycles e.g.:
Index values i1_1 etc. are generated
intg1 table lookup synchronously
Intermediate tempo is generated, and intg1 is updated.
The current design does step 2. and 3. in a single cycle, whereby it is not possible to make a synchronous lookup in the table, since there is only one clock edge in the cycle, and this is used for writing back to the intg1 table. So by splitting the lookup and write back operation in two cycles, it is possible both to have a clock edge for reading the table (synchronous read) and for writing the table. Such a synchronous read using a clock edge is much more efficient based on the available hardware resources in typical FPGAs, since these contains large synchronous RAMs similar to the intg1 table, thus the implementation will be smaller and faster. The synchronous intg1 lookup is made by simply adding a clocked process where signals are driven directly by the intg1 output based in the required index values. All the required reads must be made, then the subsequent process can then determine which of the read value that are actually used.
The specific pipeline implementation must be adapted to the design requirements.
Is it possible to set an inout pin to specific value when after monitoring the value in same pin.ie if we have an inout signal then if value on that signal is one then after doing specific operation can we set value of that pin to zero in vhdl.
What you are describing doesn't make a lot of sense. Are you sure you are understanding the requirements correctly?
Your load signal sounds like an external control signal that is an input into your module. You should not be trying to change the value of that signal - whoever is controlling your module should do that instead.
As long as the load signal is asserted (1), you should probably be loading your shift register with whatever value is presumably being provided on a different input signal (e.g., parallel_data). When the load signal is deasserted (0) by the external logic, you should probably start shifting out one bit of the loaded data per clock cycle to your output signal (e.g., serial_data).
Note that there is no need for bidirectional signals!
This is all based on what I would consider typical behavior for a shift register, and may or may not match what you are trying to achieve.
This doesn't sound like a good plan, and I'm not entirely sure you want to do it, but I guess if you can set things up such that:
you have a resistor pulling the wire down to ground.
your outside device drives the wire high
the FPGA captures the pin going high and then also drives it high
The outside source goes tristate once it has seen the pin go high
the FPGA can then set the pin tristate when it wants to flag it has finished (or whatever), and the resistor will pull it low again
repeat
I imagine one use for this would be for the outside device to trigger some processing and the FPGA to indicate when it has finished, in which case, the FPGA code could be something like:
pin_name <= '1' when fpga_is_processing = '1' else 'Z';
start_processing <= '1' when pin_name = '1' and pin_name_last = '0';
pin_name_last <= pin_name when rising_edge(clk);
start processing will produce a single clock pulse on the rising edge of the pin_name signal. fpga_is_processing would be an output from your processing block, which must "come back" before he external device has stopped driving the pin high.
You may want to "denoise" the edge-detector on the pin_name signal to reduce the chances of external glitches triggering your processing. There are various ways to achieve that also.
I need develope synthesizable custom verilog code for generating a higher frequency clock from low frequency clock i.e from 50 MHz clock i need to generate 100 MHZ clock . kindly help how to do the same.
A pure Verilog solution is not stable, so dedicated FPGA resources must be used.
Please see this previous answer; it applies to Verilog also, even through tagged VHDL.