Makefiles: subdirectories and similar filenames [closed] - makefile

Question

Closed. This question needs to be more focused. It is not currently accepting answers.
Want to improve this question? Update the question so it focuses on one problem only by editing this post.
Closed 5 years ago.
Improve this question
Switched to Visual Studio Code in an effort to understand C/C++ dev tools and to stop relying on IDEs. I try to use Makefiles for this purpose because it allows to run compilation via command line on a target device (no GUI == no IDE). So far I've managed to make a generic Makefile that compiles all .cpp files to corresponding .o files and then links it all together. It works for small projects that store all sources in a single directory. Now I must port my working Xcode project.
The problem is that the source files are stored in a directory tree (no single directory) and may be both C and C++. Some files have similar filenames but reside in different folder. From C++ perspective it means classes the have same name, but different namespaces. Various IDEs handle this easily but Makefile gives me all sorts of problems cause I am not yet a make guru.
I've tried to create Makefiles in each directory (I failed), but then I read that is considered a bad approach so I switched to a single Makefile approach. Some say I should switch to CMake but I think that it is pointless without understanding the Makefile creation first because CMake would eventually create one. It would also allow to build and install on devices without CMake and other cool tools (if, for example, there is no Internet connection to download CMake).
Here is a basic idea:
- project-name/
- application/
- core/
- loader.hpp
- loader.cpp
- ...
- loader.hpp
- loader.cpp
- ...
- hardware/
- loader.hpp
- loader.cpp
- ...
- some-c-library
- library.h
- library.c
- ...
- main.cpp
- project-name.xcodeproj
- Makefile
TR&DL: Unable to make complicated Makefile. GNU manual is hard to understand and online blogs/tutorials mostly touch only basic stuff.

Answer 1

I'm really not sure you need to be overly complicated. Sure, you could have the Makefile hunt down your directory tree for every C and C++ file, but what if you've added a new file that you don't want compiled just yet?
You can make things easier without being too complicated though. Assign the list of source files to variables - that way you can refer to them whenever you need them.
CPPSOURCES=hardware/loader.cpp application/core/loader.cpp main.cpp
CSOURCES=some-c-library/library.c
Then you convert those filenames into object filenames - this is just doing a replace of .cpp with .o etc...
CPPOBJS=$(CPPSOURCES:.cpp=.o)
COBJS=$(CSOURCES:.c=.o)
And there are standard variables that make uses for specifying what flags to pass to the C++ and C compilers
CXXFLAGS-g
CFLAGS-g
Then you have a rule to build your project. $# is the name of the thing the rule is building (ie "myproject") and $^ is the list of dependencies.
myproject: $(COBJS) $(CPPOBJS)
$(CXX) $(CXXFLAGS) -o $# $^
Make comes with a bunch of default rules so that it already knows that if you ask it to build "some/where/deep/in/my/project/somefile.o" that it's looking for "some/where/deep/in/my/project/somefile.cpp" for example.
You could add a rule to delete all the object files - this is why using variables comes is handy
clean:
rm $(COBJS) $(CXXOBJS)
The only other thing you'll need to worry about are dependencies, like the below example which tells make that it needs to build "hardware/loader.o" whenever "hardware/loader.hpp" or "application/core/loader.hpp" are newer.
hardware/loader.o: hardware/loader.hpp application/core/loader.hpp
This is probably the one area where you want to investigate automatically generation as it's very easy to miss out a dependency and then it won't pick up any changes in the headers. As noted in the comments, gcc/g++ can generate files with them in for you when you build the code using the -M command line options which you can use the include directive in the Makefile to add them.