While creating project in Xilinx ISE, we have to select a package in project setting after choosing Family and device. Could any one help me, how I can select/know the package in Xilinx ISE project setting for FPGA Spartan 3 Device XC3S200. Thanks in advance
The XC3S200 is available in four different physical IC packages -- the VQG100, TQG144, PQG208, and FTG256 packages. Each of these packages has a different number of pins, so ISE needs to know which one you are using.
We have no way of knowing which package your board is using -- you'll need to look at the board yourself. The package type will be printed on the surface of the FPGA. For example, here's how it would be printed on the FTG256 package (from Spartan-3 FPGA Family: Introduction and Ordering Information):
If you don't have a board yet and you just need to start a project for testing, pick a package arbitrarily. You can change it later.
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I need a list of device-specific primitives of Xilinx devices. I know that ISE has a list of templates and there are also PDF user guides but I need them as list of files in a folder so that I can parse them and extract name and port-list of every module.
Any help will be appreciated.
If you are using Xilinx ISE take a look at the folder "C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\unisims\primitive" (default install location, version may vary).
In this folder you will find VHDL files for all Xilinx primitives, not sorted by device however.
Look for the file named unisim_VCOMP.vhd. It has all the component declarations of the Xilinx primitives.
For ISE, this is located at
[install dir]\[version]\ISE_DS\ISE\vhdl\src\unisims
For Vivado,
[install dir]\[version]\data\vhdl\src\unisims
Note, for Vivado, if you have VHDL that has primitives from older devices, then use unisim_retarget_VCOMP.vhd, which retargets old primitives to 7 Series and Ultrascale equivalents. However, there are some cases when retargeting certain primitives is not possible.
If your code is for 7 Series and Ultrascale families, I wouldn't worry about the "retarget" file.
I have almost found what I wanted. Language templates are stored in location:
[install dir][version]\ISE_DS\ISE\data\projnav\templates
I'm new to fpga programming, and I'm wondering how to make my fpga design distributable. Here's the scenario I have in mind. I have a network of computers, each deployed with an fpga based peripheral. I want to update the fpga design on the peripherals periodically. How do I accomplish this without spending a fortune on software licenses?
I have a small dev kit for an fpga that shipped with an executable to load example design files (it was an Altera fpga FYI). Does anyone know how I would create such an executable?
Some specifics:
My fpgas are Xilinx Spartan 6Es. I'm using Xilinx ISE for fpga development. The host computers are running debian linux.
Thanks for any and all advice!
If youre dealing with Altera: one computer would have the software tools and licenses needed to synthesize the project. Assuming all the FPGAs are the same model on each station/node, Quartus will generate an .sof file which you can copy and open from station to station. All you would need to do is download the Altera programmer tool (I believe you can download it separately from Quartus II) on each station which is free. Then upload the .sof to the board using the programmer, where you can permanently store it on the fpga prom using a technique similar to the following:
https://m.youtube.com/watch?v=ZrMe8JS7Ktk
However if you have Xilinx and Altera mix, Xilinx has .bit/xdl files, and uses another tool (impact) to upload their bitstreams. They can't be converted to and from bit and sof. So it's recommended that you probably stick to one make (Xilinx or Altera) and model based on your plans.
It looks like what you are looking for is how to make your FPGA's field upgradable. Assuming your FPGA is loading from an external memory such as an SPI flash chip, then you need to modify your design so that it is capable of writing to the SPI chip (or whatever) itself. This is most simply done by putting a register in your design which maps to the individual pins on the flash chip, and then "bit bang" the register from a connected computer. Assuming your FPGAs feed data into your own software running on the computer, then you would modify this software to have the functionality of manipulating this register to reflash the flash device. Obviously, if this goes wrong you bricked your device until it can be flashed again with the JTAG, but it provides a way for all the devices to get updated in the systems they operate without needing to buy a JTAG cable for every single station.
If you have Ethernet on your board you can use the remote programming tool from fpga-cores.
Then you can remote login to the network and program the FPGAs or mail the new config file to you customer and they run the programmer. This is how we remotely updates our boards.
Spartan 6 is supported. As a bonus you can also do some remote debugging with the remote logic analyzer.
Everything is free for non commercial use.
I am using the excellent open-source FPGALink utility to program a FPGA, through USB and JTAG.
Classically, I generate a .bit file correctly, using a set of scripts gluing the various stages of the Xilinx synthesis process.
That works like a charm : just after the bitstream has been loaded into FPGA, I can play with my embedded design on a Nexys2 FPGA board (from Digilent).
However, now I am facing a new challenge : I'd like to flash my .bit file into the PROM. It seems I need to generate a .mcs file now. I found a tutorial but it focuses on Xilinx GUI, that I really want to avoid.
How can I manage to do this, only based on scripts ? (update : this link seems to give a detailed procedure)
And then how to load this in PROM, using FPGALink ?
It seems that everything is explained here.
I have xilinx macros for uart (.edn files) and i don't know how to use the in activehdl
when i simulate the macros the give uninitialized output ? so what if any one can help me with the right way to use the macro ...?
Use the Xilinx uniMacro library. You may need to compile or download it for your simulator.
ActiveHDL is a simulator package. It typically operates by compile VHDL or Verilog code. The "macros" you are refering to with the extension ".edn" are EDIF netlist files. These are not files that can typically be used by simulator, but are in almost all cases only usable by the synthesizer for the exact device they are targeting.
It may be the case that ActelHDL can import EDIF files. In this case, it still will only work if the primitives used by the EDIF file are also added as part of the project. As another answer said, this most likely would be primitives from the Xilinx unisim library.
The best option is to probably run the EDIF files you have through the Xilinx tools (specifically "Translate" (ngdbuild) and "Generate Simulation Netlist" (netgen)) to generate a simulation model for these pieces. The result will likely require the Xilinx unisim and simprims libraries, which are usually available precompiled for most simulators, but can also easily just be pointed to the source in the Xilinx ISE install.
My company is trying to build a pcb with an obsolete xilinx fpga (XC3042A) which is part of the XC3000 series chips. Does anyone have any experience programming the data to the chip? I'm looking for what software, hardware, etc. people have used.
I have programmed old Xilinx chips (XC4010XL) using a custom built interface to the ISA bus.
I used Turbo-C on a DOS box and a home-made ISA card with '245 (bidir transceiver) and a 74LS74 (dual flip flop D) for strobe signals on a slave parallel configuration.
It is not difficult to implement the same using a parallel port, for instance.
You should be able to find the programming specs from the Xilinx website. They provide documentation on the different methods used in programming their FPGA. It should be in their AppNotes. They have several modes - typically slave serial or select map (parallel). That means some sort of SPI flash, or parallel flash, or JTAG.
If you look around, you may find schematics for a DIY programming cable too! You can also interface a small micro, say a 8-bit PIC to handle the programming specs while you design your own custom interface to it or interface it to a SD card or something else.
The current Xilinx tools and cables will program old parts.
The XC3000 series does not use the JTAG interface, so you can not use the Xilinx programmer to download your configuration.
You can do so by either using an external EPROM or an embedded processor to download the code.
Take a look at this applications note from Xilinx:
http://www.xilinx.com/support/documentation/application_notes/xapp090.pdf
For daisy chain:
http://www.xilinx.com/support/documentation/application_notes/xapp091.pdf
It describes the data format as well as signal info for downloading the configuration file to the FPGA.
You can use older version of the Xilinx programmer from their web site and configure the devices, I believe the last version of the xilinx supporting the 3000 series was version 8 but I am not sure.
Check out FTDI. You might be able to convince them to go with some updated hardware. It's currently $150 CAD for USB + FPGA, and $80 CAD extra if you bundle it with a Manual. Plus shipping.
It even supports the free web kit available from the Xilinx website.