I have sliced a 16 bit STD_LOGIC_VECTOR into 3 parts. I want to leave the first 8 MSBs untouched and break the 8 LSBs into 2 nibbles to do some processing on them.
I can do all this and the processing is all fine but when I try to put them all together into a 16 bit STD_LOGIC_VECTOR output it just stays UUUU. is there a special way that putting it back together should go?
signal fullout : std_logic_vector(15 downto 0);
signal Sbox1 : integer;
signal Sbox2 : integer;
signal tophalf : std_logic_vector(7 downto 0);
signal secondnibble, firstnibble : std_logic_vector(3 downto 0); --break the LSH into 2 nibbles
begin
tophalf(7 downto 0) <= LUTin(15 downto 8);
secondnibble(3 downto 0) <= LUTin(7 downto 4);
-- Sbox1 <= to_integer(unsigned(secondnibble));
firstnibble(3 downto 0) <= LUTin(3 downto 0);
-- Sbox2 <= to_integer(unsigned(firstnibble));
p1: process(LUTin)
begin
fullout(15 downto 8) <= tophalf(7 downto 0);
fullout(7 downto 4) <= secondnibble(3 downto 0);
fullout(3 downto 0) <= firstnibble(3 downto 0);
Always initialize outputs. In your case, its not clear that what is output, so here is my guess:
architecture xyz of zyx is
signal fullout : std_logic_vector(15 downto 0) := (others =>'0');
signal tophalf : std_logic_vector(7 downto 0):= (others =>'0');
signal secondnibble, firstnibble : std_logic_vector(3 downto 0):= (others =>'0');
.....
begin
....
end xyz;
Related
My code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.costanti.all;
entity Multiplier is
generic(nbA:integer:=nbA;
nbB:integer:=nbB);
port (
A: in STD_LOGIC_VECTOR(nbA-1 downto 0);
B: in STD_LOGIC_VECTOR(nbB-1 downto 0);
clk: in STD_LOGIC;
R: out STD_LOGIC_VECTOR(nbA+nbB-1 downto 0));
end Multiplier;
architecture Behavioral of Multiplier is
component AdderTree is
generic(nbit: integer:=nbA+nbB);
port (
IN1: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN2: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN3: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN4: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN5: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN6: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN7: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN8: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN9: in STD_LOGIC_VECTOR(nbit-1 downto 0);
S: out STD_LOGIC_VECTOR(nbit-1 downto 0)
);
end component;
signal V : STD_LOGIC_VECTOR(nbA-1 downto 0);
signal P : STD_LOGIC_VECTOR((nbA*nbB)-1 downto 0);
signal PP_0to6 : STD_LOGIC_VECTOR( (nbA)+(nbA+1)+(nbA+2)+(nbA+3)+(nbA+4)+(nbA+5)+(nbA+6)-1 downto 0); --(dim(pp0+PP1+PP2+PP3+PP4+PP5+PP6) downto 0 )
signal PP7 : STD_LOGIC_VECTOR(nbA+nbB-1 downto 0);
signal P7 : STD_LOGIC_VECTOR(nbA downto 0);
signal PPP : STD_LOGIC_VECTOR((nbA+nbB)*(nbB+1)-1 downto 0);
begin
for_g: for i in 0 to nbB-1 generate
V <= (others => B(i));
P((nbB)*(i)+(nbB-1) downto (nbB)*(i)) <= V and A;
end generate for_g;
P7 <= '0' & P((nbA*nbB)-1 downto (nbA*nbB)-1-(nbB-1));
PP_0to6(nbB-1 downto 0) <= P(nbB-1 downto 0); --PP0
for_g2: for i in 0 to nbB-3 generate
PP_0to6((nbB+1)*(i+1)+(i*(i+1)/2)+7 downto (nbB+1)*(i+1)+(i*(i+1)/2)) <= P(nbB*(i+1)+(nbB-1) downto nbB*(i+1)); --PP1 to PP6
PP_0to6((nbB+1)*(i+1)+(i*(i+1)/2)-1 downto (nbB+1)*(i)+((i-1)*(i)/2)+7+1) <= (others => '0');
end generate for_g2;
PP7(nbA+nbB-1 downto nbA-1) <= P7;
PP7(nbA-2 downto 0) <= (others => '0');
PPP_0to6: for i in 3 to nbB-2 generate
PPP(((i+1)*(nbA+nbB-1)+i)-(8-i) downto i*(nbA+nbB)) <= PP_0to6( (i+1)*(nbB-1)+((1/2)*((i*i)+(3*i))) downto i*(nbB)+(i-1)*i/2); --PP0 to PP6
PPP(((i+1)*(nbA+nbB-1)+i) downto ((i+1)*(nbA+nbB-1)+i)-(8-i)+1)<= (others => '0');
end generate PPP_0to6;
-- Fill last 32 bits of PPP
--Insert ADDER TREE
end Behavioral;
Portion of the error code: portion of code
PPP_0to6: for i in 0 to nbB-2 generate
PPP(((i+1)*(nbA+nbB-1)+i)-(8-i) downto i*(nbA+nbB)) <= PP_0to6( (i+1)*(nbB-1)+((1/2)*((i*i)+(3*i))) downto i*(nbB)+(i-1)*i/2); --PP0 to PP6
PPP(((i+1)*(nbA+nbB-1)+i) downto ((i+1)*(nbA+nbB-1)+i)-(8-i)+1)<= (others => '0');
end generate PPP_0to6;
Hi, I'm making a multiplier on vhdl, but on line 66 it reports me the following error:
if i=1: [Synth 8-690] width mismatch in assignment; target has 9 bits, source has 7 bits ["...Multiplier.vhd":66]
if i=2: [Synth 8-690] width mismatch in assignment; target has 10 bits, source has 5 bits ["...Multiplier.vhd":66]
if i=3: [Synth 8-690] width mismatch in assignment; target has 11 bits, source has 2 bits ["...Multiplier.vhd":66]
and so on..
I can't understand why, they seem to be the same size ..
my constant are:
nbA=8
nbB=8
and the signal P, PP_0to6 and PPP:
signal P : STD_LOGIC_VECTOR((nbA*nbB)-1 downto 0);
signal PP_0to6 : STD_LOGIC_VECTOR( (nbA)+(nbA+1)+(nbA+2)+(nbA+3)+(nbA+4)+(nbA+5)+(nbA+6)-1 downto 0);
signal PPP : STD_LOGIC_VECTOR((nbA+nbB)*(nbB+1)-1 downto 0);
N.B. I make sure to shift to the rigth by adding zeros as in the figure:
schema
The error is here:
PPP(((i+1)*(nbA+nbB-1)+i)-(8-i) downto i*(nbA+nbB)) <= PP_0to6( (i+1)*(nbB-1)+((1/2)*((i*i)+(3*i))) downto i*(nbB)+(i-1)*i/2);
but if I tried to replace the value of i:
i=0: PPP(7 downto 0) <= PP_0to6(7 downto 0);
i=1: PPP(24 downto 16)<=PP_0to6(16 downto 8)
i=2: PPP(41 downto 32)<=PP_0to6(26 downto 17)
i=3: PPP(58 downto 48)<=PP_0to6(37 downto 27)
...
...
the dimensions look the same.
I guess strictly speaking this answer doesn't really answer your question, since I'm not trying to figure out where your error is. But I'm convinced that if you change your coding style you won't encounter such difficult to debug errors any more.
As mentioned in my comments, your code will become must clearer and easier to debug if you split the signal up properly. I.e. don't create one giant signal for everything.
VHDL has arrays and records, use them, they won't make your circuit any larger, but the code will be much easier to reason about.
It's been a while since I actually wrote VHDL, so the syntax below might contain typo's, but hopefully the idea behind the code is clear:
constant c_AllZeros : std_logic_vector(c_MaxZeros - 1 downto 0) := (others => '0');
...
type t_P is std_logic_vector(c_SomeLength - 1 downto 0);
subtype t_P_Array is array (natural range <>) of t_P;
...
signal P : t_P_Array(0 to c_NumInputs - 1);
...
PPP_0to6: for i in PPP'range generate
PP(i) <= P(i) & c_AllZeros(index downto 0);
PPP(i) <= c_AllZeros(c_MaxZeros - index downto 0) & PP(i);
end generate PPP_0to6;
As you might notice, I also got rid of the explicit indices for the for-loop in the generate. There's still a magic number when indexing the all_zeroes signal to generate PPP. If I was writing this code, I'd replace that with some (calculated) constant with a meaningful name. This will make the code both more readable and trivial to change later on.
Note that there's other ways to do this. E.g. you could first set all bits of all PP signals to 0 and then assign a slice of them the P value.
I am learning VHDL through a project and I would like to transform a binary number into a decimal number (also expressed in binary). I need to do so because I am printing the number in decimal and if I try to print it without converting it I obtain an hexadecimal number...
For example
I have 0010 1010 1111 0001 (2AF1) and I want 0001 0000 1001 1001 0011 (10993)
I must precise that my binary number is on 32 bits
It must be very simple because I can't find the solution on the internet ...
EDIT : This code is working and transform a binary number into a decimal number expressed in binary (d'10 = b'0001 0000)
signal val0 : std_logic_vector(31 downto 0);
signal val1 : std_logic_vector(31 downto 0);
signal val2 : std_logic_vector(31 downto 0);
signal val_Mux : std_logic_vector(31 downto 0);
val_MUX <= std_logic_vector(unsigned(val0)+1) when cpt50M_Comp = '1' else val0;
val1(3 downto 0)<= val_MUX(3 downto 0);
loopA:
for i in 0 to 6 generate
val1(4*i+7 downto 4*i+4) <= std_logic_vector(unsigned(val_MUX(4*i+7 downto 4*i+4))+1) when val1(4*i+3 downto 4*i) > "1001"
else val_MUX(4*i+7 downto 4*i+4);
val2(4*i+3 downto 4*i) <= "0000" when val1(4*i+3 downto 4*i) > "1001"
else val1(4*i+3 downto 4*i);
end generate loopA;
val2(31 downto 28)<= val1(31 downto 28);
val0 <= (others => '0') when reset='1' else
val2 when rising_edge(clk50);
The solution was to go through 2 others signal before assigning the one display and assign the counter with the one display as done below :
signal val0 : std_logic_vector(31 downto 0);
signal val1 : std_logic_vector(31 downto 0);
signal val2 : std_logic_vector(31 downto 0);
signal val_Mux : std_logic_vector(31 downto 0);
val_MUX <= std_logic_vector(unsigned(val0)+1) when cpt50M_Comp = '1' else val0;
val1(3 downto 0)<= val_MUX(3 downto 0);
loopA:
for i in 0 to 6 generate
val1(4*i+7 downto 4*i+4) <= std_logic_vector(unsigned(val_MUX(4*i+7 downto 4*i+4))+1) when val1(4*i+3 downto 4*i) > "1001"
else val_MUX(4*i+7 downto 4*i+4);
val2(4*i+3 downto 4*i) <= "0000" when val1(4*i+3 downto 4*i) > "1001"
else val1(4*i+3 downto 4*i);
end generate loopA;
val2(31 downto 28)<= val1(31 downto 28);
val0 <= (others => '0') when reset='1' else
val2 when rising_edge(clk50);
The following code contains a vhdl file and a test bench for it.
Main file
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lici is
port(PT_MSB : in std_logic_vector(31 downto 0);
PT_LSB: in std_logic_vector( 31 downto 0);
--key: in std_logic_vector(127 downto 0);
RK1: in std_logic_vector(31 downto 0);
RK2: in std_logic_vector(31 downto 0);
clk: in std_logic;
CT_LSB: out std_logic_vector(31 downto 0);
CT_MSB: out std_logic_vector(31 downto 0);
check: out std_logic_vector(31 downto 0)
);
end lici;
architecture beh of lici is
type S_BOX is array(15 downto 0)of std_logic_vector(3 downto 0);
signal sub: S_BOX:=(0=>x"3",1=>x"F",2=>x"E",3=>x"1",4=>x"0",5=>x"A",6=>x"5",7=>x"8",8=>x"c",9=>x"4",10=>x"B",11=>x"2",12=>x"9",13=>x"7",14=>x"6",15=>x"D");
begin
process(clk)
Variable var_PT_MSB : std_logic_vector(31 downto 0);
variable var_PT_LSB : std_logic_vector( 31 downto 0);
variable var_EN_PT_MSB: std_logic_vector(31 downto 0);
variable var_XOR_RK_SHR7: std_logic_vector(31 downto 0);
variable var_XOR_SHL3: std_logic_vector(31 downto 0);
variable var_CT_LSB: std_logic_vector(31 downto 0);
variable S_data: std_logic_vector(3 downto 0);
variable outside_counter: natural:= 0;
variable i: natural:= 1;
begin
var_PT_MSB:= PT_MSB;
var_PT_LSB:= PT_LSB;
if(outside_counter< 31) then
if(clk'event and clk='1' and i <= 8) then
S_data:= (var_PT_MSB(31 downto 28) and x"F");
case S_data is
when x"0"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(0);
when x"1"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(1);
when x"2"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(2);
when x"3"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(3);
when x"4"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(4);
when x"5"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(5);
when x"6"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(6);
when x"7"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(7);
when x"8"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(8);
when x"9"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(9);
when x"A"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(10);
when x"B"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(11);
when x"C"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(12);
when x"D"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(13);
when x"E"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(14);
when others=>var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(15);
end case;
var_PT_MSB:= std_logic_vector(shift_left(unsigned(var_PT_MSB),4));
i:=i+1;
end if;
var_XOR_SHL3:= var_EN_PT_MSB xor RK1 xor var_PT_LSB;
var_XOR_SHL3:= std_logic_vector(rotate_left(unsigned(var_XOR_SHL3),3));
var_XOR_RK_SHR7:= var_EN_PT_MSB xor RK2 xor var_XOR_SHL3;
CT_LSB<= std_logic_vector(rotate_right(unsigned(var_XOR_RK_SHR7),7));
var_CT_LSB:= std_logic_vector(rotate_right(unsigned(var_XOR_RK_SHR7),7));
CT_MSB<= var_XOR_SHL3;
var_PT_MSB:= var_XOR_SHL3;
var_PT_LSB:= var_CT_LSB;
check<= var_EN_PT_MSB;
outside_counter:= outside_counter+1;
end if;
end process;
end beh;
--------------------------------------------------------------------------
This is the test bench for it
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lici_tb is
end lici_tb;
architecture behav of lici_tb is
component lici is
port(PT_MSB : in std_logic_vector(31 downto 0);
PT_LSB: in std_logic_vector( 31 downto 0);
RK1: in std_logic_vector(31 downto 0);
RK2: in std_logic_vector(31 downto 0);
clk: in std_logic;
CT_LSB: out std_logic_vector (31 downto 0);
CT_MSB: out std_logic_vector(31 downto 0);
check: out std_logic_vector(31 downto 0)
);
end component;
signal clk :std_logic := '0';
signal PT_MSB:std_logic_vector(31 downto 0):=x"ABCDEF01";
signal PT_LSB:std_logic_vector( 31 downto 0):=x"23456789";
signal RK1:std_logic_vector(31 downto 0):=x"00000010";
signal RK2:std_logic_vector(31 downto 0):= x"00000001";
signal CT_LSB:std_logic_vector(31 downto 0);
signal CT_MSB: std_logic_vector(31 downto 0);
signal check: std_logic_vector(31 downto 0);
constant CLK_PERIOD : time := 10 ns;
begin
uut : lici port map (
PT_MSB => PT_MSB,
PT_LSB=>PT_LSB,
RK1=>RK1,
RK2=> RK2,
clk => clk,
CT_LSB=>CT_LSB,
CT_MSB => CT_MSB,
check=>check
);
Clk_process :process
begin
clk <= '0';
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
clk <= '1';
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
end process;
end;
At the end I need to have 31 values in CT_LSB and CT_MSB.
In each cycle I wish to have different encrypted values in CT_LSB and CT_MSB,
In one cycle one iteration of outside_counter needs to happen in which 8 NIBBLE has to encrypted.
This entire code needs to work without using a For Loops.
Can someone help me with this?
Here is my assignment for class. Our task will be to design a VHDL component that provides basic stop watch functionality. Your design should start at zero and be able to count up to 20 on the right-most 7-segment displays (the other two displays should be blank except as noted below). Pressing the center button causes the count to start and stop. The down button resets the counter to 00. If the count reaches 20, the 16 leds on the board will create a complex victory pattern.
How would I display two numbers on different numbers on two different 7segs at the same time.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity lab_3 is
Port (
-------------led output-------------------------------------
led: out std_logic_vector(15 downto 0);
-------------button inputs----------------------------------
btnc: in std_logic;
btnd: in std_logic;
-----------7 seg outpus--------------------------------------------
seg: out std_logic_vector(6 downto 0); --MSB=a: LSB=g
-------------7 seg enables----------------------------------------
an: out std_logic_vector(3 downto 0)
);
end lab_3;
architecture Behavioral of lab_3 is
------decimal seven segment display--------------------------CONSTANTS
constant ZERO_7SEG: std_logic_vector(6 downto 0) := "1000000";
constant ONE_7SEG: std_logic_vector(6 downto 0) := "1111001";
constant TWO_7SEG: std_logic_vector(6 downto 0) := "0100100";
constant THREE_7SEG: std_logic_vector(6 downto 0) := "0110000";
constant FOUR_7SEG: std_logic_vector(6 downto 0) := "0011001";
constant FIVE_7SEG: std_logic_vector(6 downto 0) := "0010010";
constant SIX_7SEG: std_logic_vector(6 downto 0) := "0000010";
constant SEVEN_7SEG: std_logic_vector(6 downto 0) := "1111000";
constant EIGHT_7SEG: std_logic_vector(6 downto 0) := "0000000";
constant NINE_7SEG: std_logic_vector(6 downto 0) := "0010000";
constant TEN_7SEG: std_logic_vector(6 downto 0) := "1000000";
constant ELEVEN_7SEG: std_logic_vector(6 downto 0) := "1111001";
constant TWELVE_7SEG: std_logic_vector(6 downto 0) := "0100100";
constant THIRTEEN_7SEG: std_logic_vector(6 downto 0) := "0110000";
constant FOURTEEN_7SEG: std_logic_vector(6 downto 0) := "0110001";
constant FIFTEEN_7SEG: std_logic_vector(6 downto 0) := "0010010";
constant SIXTEEN_7SEG: std_logic_vector(6 downto 0) := "0000010";
constant SEVENTEEN_7SEG: std_logic_vector(6 downto 0) := "1111000";
constant EIGHTEEN_7SEG: std_logic_vector(6 downto 0) := "0000000";
constant NINETEEN_7SEG: std_logic_vector(6 downto 0) := "0010000";
constant TWENTY_7SEG: std_logic_vector(6 downto 0) := "1111001";
-------------------led dance-------------------------------------- ` constant step_one: std_logic_vector(15 downto 0):="0000000000000001";`
constant step_two: std_logic_vector(15 downto 0):="0000000000000010";
constant step_three: std_logic_vector(15 downto 0):="0000000000000100";
constant step_four: std_logic_vector(15 downto 0):="0000000000001000";
constant step_five: std_logic_vector(15 downto 0):="0000000000010000";
constant step_six: std_logic_vector(15 downto 0) :="0000000000100000";
constant step_seven: std_logic_vector(15 downto 0) :="0000000001000000";
constant step_eight: std_logic_vector(15 downto 0) :="0000000010000000";
constant step_nine: std_logic_vector(15 downto 0) :="0000000100000000";
constant step_ten: std_logic_vector(15 downto 0) :="0000001000000000";
constant step_eleven: std_logic_vector(15 downto 0):="0000010000000000";
constant step_twelve: std_logic_vector(15 downto 0):="0000100000000000";
constant step_thirteen: std_logic_vector(15 downto 0):="0001000000000000";
constant step_fourteen: std_logic_vector(15 downto 0) :="0010000000000000";
constant step_fifteen: std_logic_vector(15 downto 0) :="0100000000000000";
constant step_sixteen: std_logic_vector(15 downto 0):="1000000000000000";
---------------------active constants-----------------------------------
constant active: std_logic :='1';
constant inactive: std_logic :='0';
constant ACTIVE_RESET: std_logic := '0';
constant TERMINAL_VALUE: integer := 50000000;
-------------------internal connections-------------------------SIGNALS
signal Clock: std_logic;
signal Count: unsigned(7 downto 0);
signal DividedClock: std_logic;
signal Digit0: std_logic_vector(6 downto 0);
signal Digit1: std_logic_vector(6 downto 0);
signal DigitSelect: std_logic;
signal led_dance: std_logic_vector( 15 downto 0);
-----------------clock divider----------------------------
begin
process(Clock)
variable counter: integer range 0 to TERMINAL_VALUE;
begin
if (btnD=ACTIVE_RESET) then
counter := 0;
elsif (rising_edge(Clock)) then
counter := counter + 1;
if (counter = TERMINAL_VALUE) then
counter := 0;
DividedClock <= not DividedClock;
end if;
end if;
end process;
--------------------------counter-----------------------------
process(Clock)
begin
if (btnD=active) then
count <= "00000000";
elsif (rising_edge(Clock)) then
count <= count + 1;
end if;
end process;
-------------------BCD to 7seg--------------------------------
with count select
Digit0 <= ZERO_7SEG when "0000000",
ONE_7SEG when "0000001",
TWO_7SEG when "0000010",
THREE_7SEG when "0000011",
FOUR_7SEG when "0000100",
FIVE_7SEG when "0000101",
SIX_7SEG when "0000110",
SEVEN_7SEG when "0000111",
EIGHT_7SEG when "0001000",
NINE_7SEG when "0001001",
TEN_7SEG when "0001010",
ELEVEN_7SEG when "0001011",
TWELVE_7SEG when "0001100",
THIRTEEN_7SEG when "0001101",
FOURTEEN_7SEG when "0001110",
FIFTEEN_7SEG when "0001111",
SIXTEEN_7SEG when "0010000",
SEVENTEEN_7SEG when "0010001",
EIGHTEEN_7SEG when "0010010",
NINETEEN_7SEG when "0010011",
TWENTY_7SEG when others;
with count select
Digit1 <= ZERO_7SEG when "0000000",
ZERO_7SEG when "0000001",
ZERO_7SEG when "0000010",
ZERO_7SEG when "0000011",
ZERO_7SEG when "0000100",
ZERO_7SEG when "0000101",
ZERO_7SEG when "0000110",
ZERO_7SEG when "0000111",
ZERO_7SEG when "0001000",
ZERO_7SEG when "0001001",
TWO_7SEG when "0010100",
ONE_7SEG when others;
end Behavioral;
I suppose you need to connect either the Digit0 or Digit1 signal to the seg output port.
From my experience with such displays I assume that all four digits will show the pattern encoded by seg. In order to display different patterns for each digit, the idea is to quickly turn the individual digits on and off using the an output, so that only one of them is on at any given moment, while switching seg between Digit0 and Digit1 at the same time.
If the switching is done quick enough, it will not be apparent to the eye.
There are several design examples including SSDs at vhdl.us.
Here's the full error: ERROR:HDLParsers:808 - "C:/Users/vROG/Desktop/.../CacheController.vhd" Line 72. = can not have such operands in this context.
I'd understand how to fix this if I was used '+' or '*', but equal sign?
As you can tell, the code isn't nearly being close to completely, but I can't understand why my second nested if isn't working. I've tried turning dirtyBIT to type int, but it still gives me the same error, which leads me to believe that I made a trivial error somewhere.
FIXED (Using user1155120's advice) However how do I resolve the issue with offset and tag?
architecture Behavioral of CacheController is
signal tagFROMCPU : STD_LOGIC_VECTOR(7 downto 0) := CPU_addr(15 downto 8);
signal indexFROMCPU: STD_LOGIC_VECTOR(2 downto 0) := CPU_addr(7 downto 5);
signal offsetFROMCPU: STD_LOGIC_VECTOR(4 downto 0) := CPU_addr(4 downto 0);
TYPE STATETYPE IS (state_0, state_1, state_2, state_3);
SIGNAL present_state : STATETYPE;
--Variables
signal dirtyBIT: std_logic_vector (7 downto 0);
signal validBIT: std_logic_vector (7 downto 0);
TYPE tag is array (7 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
TYPE offset is array (7 downto 0) of STD_LOGIC_VECTOR(4 downto 0);
signal myTag: tag;
signal myOFFSET : offset;
begin
--STATE MACHINE
process(clk)
begin
if (present_state = state_0) then --Start State : Checks for HIT or MISS, PERFORMS HIT OPERATION or MOVES TO STATE_1
if ((myTag(to_integer(unsigned(indexFROMCPU)) = tagFROMCPU)) then
--HIT
else
present_state <= state_1;
end if;
elsIF (present_state = state_1) then --CHECKS DIRTY BIT. IF 0, LOADS DATA, MOVES TO STATE_0 ELSE move to state_2
if (dirtyBit(to_integer(unsigned(indexFROMCPU))) = '0') then
present_state <= state_0;
else
present_state <= state_2;
end if;
elsIF(present_state = state_2) then -- DIRTY BIT IS 1, SAVES DATA, goes back to STATE_1
present_state <= state_1;
end if;
end process;
end Behavioral;
OLD CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CacheController is
Port (
clk : in STD_LOGIC;
CPU_addr : in STD_LOGIC_VECTOR (15 downto 0);
CPU_WR_RD : in STD_LOGIC;
CPU_CS : in STD_LOGIC;
CPU_RDY : out STD_LOGIC;
SDRAM_Addr : out STD_LOGIC_VECTOR (15 downto 0);
SDRAM_WR_RD : out STD_LOGIC;
SDRAM_MSTRB : out STD_LOGIC;
MUX1,MUX2 : out STD_LOGIC;
SRAM_Addr : out STD_LOGIC_VECTOR (7 downto 0);
SRAM_WEN : out STD_LOGIC
);
end CacheController;
architecture Behavioral of CacheController is
signal tagFROMCPU : STD_LOGIC_VECTOR(7 downto 0) := CPU_addr(15 downto 8);
signal indexFROMCPU: STD_LOGIC_VECTOR(2 downto 0) := CPU_addr(7 downto 5);
signal offsetFROMCPU: STD_LOGIC_VECTOR(4 downto 0) := CPU_addr(4 downto 0);
TYPE STATETYPE IS (state_0, state_1, state_2, state_3);
SIGNAL present_state : STATETYPE;
--Variables to emulate SRAM
TYPE dirtyBIT is array (7 downto 0) of std_logic;
TYPE validBIT is array (7 downto 0) of std_logic;
TYPE tag is array (7 downto 0,7 downto 0) of std_logic;
TYPE offset is array (7 downto 0,4 downto 0) of std_logic;
begin
--STATE MACHINE
process(clk)
begin
if (present_state = state_0) then --Start State : Checks for HIT or MISS, PERFORMS HIT OPERATION or MOVES TO STATE_1
elsIF (present_state = state_1) then --CHECKS DIRTY BIT. IF 0, LOADS DATA, MOVES TO STATE_0 ELSE move to state_2
if (dirtyBit(to_integer(unsigned(indexFROMCPU))) = '0') then
present_state <= state_0;
else
present_state <= state_2;
end if;
elsIF(present_state = state_2) then -- DIRTY BIT IS 1, SAVES DATA, goes back to STATE_1
present_state <= state_1;
end if;
end process;
end Behavioral;
Operator overload resolution (for the "=" operator) requires a function be declared with a matching signature (types of the left and right inputs and the return type).
if (dirtyBit(to_integer(unsigned(indexFROMCPU))) = '0') then
Change the declaration for dirtyBit:
--Variables to emulate SRAM
-- TYPE dirtyBIT is array (7 downto 0) of std_logic;
signal dirtyBIT: std_logic_vector (7 downto 0);
And your code analyzes. I'd suggest the other type declaration (validBIT, tag and offset) should be similarly treated.
It looks like there should be an array type where offset is used. The type name might be changed to preserve offset as a signal name.