Is this a look ahead adder? And how to benchmark it? - vhdl

Question

I was trying to make both, the ripple carry and the look ahead N-bits adder, when I made the N-bits full-adder I decided to reuse it to the look ahead, but just doesn't feels right to me.
Full adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FullAdder is
Port (
FA_A : in STD_LOGIC;
FA_B : in STD_LOGIC;
FA_Cin : in STD_LOGIC;
FA_S : out STD_LOGIC;
FA_Cout : out STD_LOGIC
);
end FullAdder;
architecture Behavior of FullAdder is
begin
FA_S <= FA_A XOR FA_B XOR FA_Cin ;
FA_Cout <= (FA_A AND FA_B) OR (FA_Cin AND FA_A) OR (FA_Cin AND FA_B);
end Behavior;
The N-bits block:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FullAdderNBits is
Generic( N : integer := 8 );
Port (
A : in STD_LOGIC_VECTOR(0 to N-1);
B : in STD_LOGIC_VECTOR(0 to N-1);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR(0 to N-1);
Cout : out STD_LOGIC
);
end FullAdderNBits;
architecture Behavior of FullAdderNBits is
signal temp_B : STD_LOGIC_VECTOR(0 to N-1);
signal carries : STD_LOGIC_VECTOR(0 to N);
component FullAdder Port(
FA_A : in STD_LOGIC;
FA_B : in STD_LOGIC;
FA_Cin : in STD_LOGIC;
FA_S : out STD_LOGIC;
FA_Cout : out STD_LOGIC
);
end component;
begin
temp_B <= not B when Cin = '1' else B;
carries(N) <= Cin;
ForGenerate: for i in (N-1) downto 0 generate
UX: FullAdder port map(
A(i),
temp_B(i),
carries(i+1),
S(i),
carries(i)
);
end generate ForGenerate;
Cout <= carries(0);
end Behavior;
Look Ahead:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LookAheadAdder is
Port (
LAA_A : in STD_LOGIC;
LAA_B : in STD_LOGIC;
LAA_Cin : in STD_LOGIC;
LAA_S : out STD_LOGIC;
LAA_Cout : out STD_LOGIC
);
end LookAheadAdder;
architecture Behavior of LookAheadAdder is
signal P : STD_LOGIC;
signal G : STD_LOGIC;
begin
P <= LAA_A xor LAA_B;
G <= LAA_A and LAA_B;
LAA_S <= P xor LAA_Cin;
LAA_Cout <= G or (P and LAA_Cin);
end Behavior;
Same N-bits block, just changed the component:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LookAheadNBitsAdder is
Generic( N : integer := 8 );
Port (
A : in STD_LOGIC_VECTOR(0 to N-1);
B : in STD_LOGIC_VECTOR(0 to N-1);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR(0 to N-1);
Cout : out STD_LOGIC
);
end LookAheadNBitsAdder;
architecture Behavior of LookAheadNBitsAdder is
signal temp_B : STD_LOGIC_VECTOR(0 to N-1);
signal carries : STD_LOGIC_VECTOR(0 to N);
component LookAheadAdder Port(
LAA_A : in STD_LOGIC;
LAA_B : in STD_LOGIC;
LAA_Cin : in STD_LOGIC;
LAA_S : out STD_LOGIC;
LAA_Cout : out STD_LOGIC
);
end component;
begin
temp_B <= not B when Cin = '1' else B;
carries(N) <= Cin;
ForGenerate: for i in (N-1) downto 0 generate
UX: LookAheadAdder port map(
A(i),
temp_B(i),
carries(i+1),
S(i),
carries(i)
);
end generate ForGenerate;
Cout <= carries(0);
end Behavior;
How can I test with one is faster? I dont have a FPGA so can I do it with ModelSim? I tried simulate but doesn't looks like the propagation make any delay, the wave just jump from a state to another.

Answer 1

Both of these are written as combinational logic. Meaning the input will immediately propagate to the output. The only way to see which is "faster" would be to introduce a clock and start counting clock cycles. You can see which would use less resources on the chip, but if they're both written in combinational logic (not sequential) then in simulation the output will be immediate.