Counter not working in FPGA - vhdl

I have a VHDL component that is connected to a UART receiver. The uart has 2 output signals, one for the byte received and one for a flag that is set to 1 when the byte is done being received.
I have written the following module that should increment a counter for every new char and show it lighting up some leds.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity test is
port (
clk : in std_logic;
rst : in std_logic;
ena : in std_logic;
rx : in std_logic;
led0 : out std_logic;
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
led4 : out std_logic;
led5 : out std_logic;
led6 : out std_logic;
led7 : out std_logic
);
end test;
architecture arch of test is
component UART_RX
generic (
g_CLKS_PER_BIT : integer := 115 -- Needs to be set correctly
);
port (
i_Clk : in std_logic;
i_RX_Serial : in std_logic;
o_RX_DV : out std_logic;
o_RX_Byte : out std_logic_vector(7 downto 0)
);
end component;
signal sig_Din : std_logic_vector(7 downto 0);
signal sig_Dout : std_logic_vector(7 downto 0);
signal sig_RxErr : std_logic;
signal sig_RxRdy : std_logic;
signal sig_TxBusy : std_logic;
signal sig_StartTx: std_logic;
begin
UUT : UART_RX
generic map (
g_CLKS_PER_BIT => 434
)
port map (
i_clk => clk,
i_rx_serial => rx,
o_rx_dv => sig_RxRdy,
o_rx_byte => sig_Dout
);
process(clk)
variable position : integer := 0;
variable position_v : std_logic_vector(7 downto 0) := "00000000";
begin
if(sig_RxRdy = '1') then
position := position + 1;
position_v := std_logic_vector((unsigned(position_v1), 1));
led0 <= position_v(0);
led1 <= position_v(1);
led2 <= position_v(2);
led3 <= position_v(3);
led4 <= position_v(4);
led5 <= position_v(5);
led6 <= position_v(6);
led7 <= position_v(7);
end if;
end process;
end arch;
Is there any problem with the implementation? Every new char i send ends up incrementing the counter by more than 1. And is not even the same value every time.
I must not be understanding how FPGAs actually work because this is simple and I can't get it to work.

You are using sig_RxRdy as condition for incrementing. But we can not see how that signal behaves as it comes out of a module for which we have no code.
From the behavior you describe the o_rx_dv output (where sig_RxRdy comes from) is likely to be high for more then one of your clk cycles. As the UART input comes from an external source the time it is high may be variable which makes that you counter increment differs.
Solution is to detect a rising edge on sig_RxRdy by using a delayed version:
prev_sig_RxRdy <= sig_RxRdy;
sig_RxRdy_rising <= sig_RxRdy and not prev_sig_RxRdy;
Then increment your counters on that signal. This only works if o_rx_dv is already synchronous to your clock.

Related

Ripple carry adder in vhdl

hi i' trying to do a 4 bit ripple carry adder with VHDL. The problem is that i'm trying to do a testbench to simulate it in ModelSim, but it doesn't work. This is the code and also the code reported by ModelSim:
Full adder code:
library ieee;
use ieee.std_logic_1164.all;
entity fullAdder is
port( -- Input of the full-adder
a : in std_logic;
-- Input of the full-adder
b : in std_logic;
-- Carry input
c_i : in std_logic;
-- Output of the full-adder
o : out std_logic;
-- Carry output
c_o : out std_logic
);
end fullAdder;
architecture data_flow of fullAdder is
begin
o <= a xor b xor c_i;
c_o <= (a and b) or (b and c_i) or (c_i and a);
end data_flow;
Ripple carry adder code:
library ieee;
use ieee.std_logic_1164.all;
entity Ripple_Carry_Adder is
Port (
A: in std_logic_vector (3 downto 0);
B:in std_logic_vector (3 downto 0);
Cin:in std_logic;
S:out std_logic_vector(3 downto 0);
Cout:out std_logic
);
end Ripple_Carry_Adder;
architecture data_flow2 of Ripple_Carry_Adder is
component fullAdder
Port(
A:in std_logic;
B:in std_logic;
Cin:in std_logic;
S:out std_logic;
Cout:out std_logic
);
end component;
signal c1,c2,c3:STD_LOGIC;
begin
FA1:fullAdder port map(A(0),B(0), Cin, S(0), c1);
FA2:fullAdder port map(A(1),B(1), c1, S(1), c2);
FA3:fullAdder port map(A(2),B(2), c2, S(2), c3);
FA4:fullAdder port map(A(3),B(3), c3, S(3), Cout);
end data_flow2;
code of Ripple carry adder testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY ripple_carry_adder_tb is
end ripple_carry_adder_tb;
ARCHITECTURE behavior OF ripple_carry_adder_tb is
constant T_CLK : time := 10 ns; -- Clock period
constant T_RESET : time := 25 ns; -- Period before the reset deassertion
COMPONENT Ripple_Carry_Adder
PORT (
A:in std_logic_vector(3 downto 0);
B:in std_logic_vector(3 downto 0);
Cin:in std_logic;
S:out std_logic_vector(3 downto 0);
Cout:out std_logic
);
END COMPONENT;
signal A_tb:std_logic_vector(3 downto 0):="0000";
signal B_tb:std_logic_vector(3 downto 0):="0000";
signal Cin_tb:std_logic:='0';
signal S_tb:std_logic_vector(3 downto 0);
signal Cout_tb:std_logic;
signal clk_tb : std_logic := '0'; -- clock signal, intialized to '0'
signal rst_tb : std_logic := '0'; -- reset signal
signal end_sim : std_logic := '1';
BEGIN
clk_tb <= (not(clk_tb) and end_sim) after T_CLK / 2; -- The clock toggles after T_CLK / 2 when end_sim is high. When end_sim is forced low, the clock stops toggling and the simulation ends.
rst_tb <= '1' after T_RESET;
RP_1: Ripple_Carry_Adder PORT MAP(A=>A_tb,B=>B_tb,Cin=>Cin_tb,S=>S_tb,Cout=>Cout_tb);
d_process: process(clk_tb, rst_tb) -- process used to make the testbench signals change synchronously with the rising edge of the clock
variable t : integer := 0; -- variable used to count the clock cycle after the reset
begin
if(rst_tb = '0') then
A_tb <= "0000";
B_tb <= "0000";
Cin_tb<='0';
t := 0;
elsif(rising_edge(clk_tb)) then
A_tb<=A_tb+1;
B_tb<=B_tb+1;
t := t + 1;
if (t>32) then
end_sim <= '0';
end if;
end if;
end process;
END;
and this is errors reported by ModelSim when i trying to start simulation:
# ** Fatal: (vsim-3817) Port "c_i" of entity "fulladder" is not in the component being instantiated.
# Time: 0 ns Iteration: 0 Instance: /ripple_carry_adder_tb/RP_1/FA1 File:
C:/Users/utente/Desktop/full_adder.vhd Line: 11
# FATAL ERROR while loading design
# Error loading design
Why doesn't work? Thanks

Quartus Prime Lite Failed to find INSTANCE

I've tryed to run a simulation with ModelSim on Quartus Prime Lite but I've got this error messages:
Error (suppressible): (vsim-SDF-3250) Counter_6_1200mv_85c_vhd_slow.sdo(0): Failed to find INSTANCE '/i1'.
Error (suppressible): (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s).
Error (suppressible): (vsim-SDF-3250) Counter_6_1200mv_85c_vhd_slow.sdo(0): Failed to find INSTANCE '/i1'
It doesn't matter which code I'm running. The compilation was succesfull and the simulation path is right.
-- The code.
-- ADC reader: reads data from ADXL345
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity g_reader is port (
clk_50: in std_logic; -- 50 MHz clock
reset_n : in std_logic; -- reset signal (active low)
-- SPI interface
CS_N : out std_logic; -- connected to chip select of g sensor
SCLK : out std_logic; -- spi clock
SDIO : inout std_logic; -- spi data (bidirectional)
-- data output
dataX : out std_logic_vector(12 downto 0);
dataY : out std_logic_vector(12 downto 0);
dataZ : out std_logic_vector(12 downto 0)
);
end g_reader;
architecture behavior of g_reader is
signal SCLK_counter : integer := 0; -- starts clock
signal SCLK_1 : std_logic; -- 1 MHz clock
constant half_period : time := 10 ns;
begin
-- SCLK
process(clk_50)
begin
if (falling_edge(clk_50)) then
if (SCLK_counter <= 24) then
SCLK_1 <= '0';
else
SCLK_1 <= '1';
end if;
if (SCLK_counter >= 49) then
SCLK_counter <= 0;
else
SCLK_counter <= SCLK_counter + 1;
end if;
end if;
end process;
CS_N <= '0';
SCLK <= '0';
dataX <= "0000000000000";
dataY <= "0000000000000";
dataZ <= "0000000000000";
end behavior;
The testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY g_reader_vhd_tst IS
END g_reader_vhd_tst;
ARCHITECTURE g_reader_arch OF g_reader_vhd_tst IS
-- constants
constant half_period : time := 10 ns;
-- signals
signal clk : std_logic := '0';
SIGNAL clk_50 : STD_LOGIC;
SIGNAL CS_N : STD_LOGIC;
SIGNAL dataX : STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL dataY : STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL dataZ : STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL reset_n : STD_LOGIC;
SIGNAL SCLK : STD_LOGIC;
SIGNAL SDIO : STD_LOGIC;
COMPONENT g_reader
PORT (
clk_50 : IN STD_LOGIC;
CS_N : OUT STD_LOGIC;
dataX : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
dataY : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
dataZ : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
reset_n : IN STD_LOGIC;
SCLK : OUT STD_LOGIC;
SDIO : INOUT STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : g_reader
PORT MAP (
-- list connections between master ports and signals
clk_50 => clk_50,
CS_N => CS_N,
dataX => dataX,
dataY => dataY,
dataZ => dataZ,
reset_n => reset_n,
SCLK => SCLK,
SDIO => SDIO
);
init : PROCESS
-- variable declarations
BEGIN
-- code that executes only once
WAIT;
END PROCESS init;
clk_proc : process
begin
clk <= not clk after half_period;
end process clk_proc;
end g_reader_arch;

lattice mackXO3 board output transient

I have a lattice MachXO3L starter kit and I'm having some trouble with inputs, I think. I'm tried reducing the code only to read 4 switches (MachXO3 Starter Kit User’s Guide page 26) and light 4 LEDs according to the state of the switch. The problem is the LEDs seem to be half off. I tried adding 'reveal' and it appears that I'm not getting any change from the switches when I expect change. I set the spreadsheet I set it the same as in the example. I'm still learning VHDL, this is the first time I'm actually trying to connect something to it and the example is on Verilog, so I can't really check what I'm doing wrong. I'm probably missing something basic, but I don't know what.
Top File:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TOP is
GENERIC(
DATAWIDTH : natural := 4
);
PORT(
-- Input Buffer --
ADCInputBuffer : IN STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0);
OUTPUT : OUT STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0);
ADC_SRT : OUT STD_LOGIC
);
end TOP;
architecture ADReader of TOP is
SIGNAL INTERNAL_CLOCK : STD_LOGIC;
SIGNAL CLOCK : STD_LOGIC;
SIGNAL CLOCK_65 : STD_LOGIC;
-- BUFFER --
signal adcInPut : std_logic_vector(DATAWIDTH-1 downto 0);
---------------------------------------------------
-- Internal Clock. Mach0X3 --
---------------------------------------------------
COMPONENT OSCH is
GENERIC(NOM_FREQ: string := "133.00"); --133.00MHz, or can select other supported frequencies
PORT(
STDBY : IN STD_LOGIC; --'0' OSC output is active, '1' OSC output off
OSC : OUT STD_LOGIC; --the oscillator output
SEDSTDBY : OUT STD_LOGIC --required only for simulation when using standby
);
END COMPONENT;
---------------------------------------------------
-- Internal Clock multiplier. Mach0X3 --
---------------------------------------------------
COMPONENT MASTERCLOCK is
PORT(
CLKI : IN STD_LOGIC; --'0' OSC output is active, '1' OSC output off
CLKOP : OUT STD_LOGIC; --the oscillator output 260MHz
CLKOS : OUT STD_LOGIC --the oscillator output for adc 65Mhz
);
END COMPONENT;
---------------------------------------------------
-- Read data In --
---------------------------------------------------
COMPONENT InputBuffer is
GENERIC(n: natural :=DATAWIDTH );
PORT(
clk : in STD_LOGIC;
CLK65 : IN STD_LOGIC;
En : in STD_LOGIC;
STRT : OUT STD_LOGIC;
Ipin : in STD_LOGIC_VECTOR (n-1 downto 0);
Output : out STD_LOGIC_VECTOR (n-1 downto 0)
);
END COMPONENT;
begin
-- System Clock
OSC: OSCH
GENERIC MAP (NOM_FREQ => "133.0")
PORT MAP (STDBY => '0', OSC => INTERNAL_CLOCK, SEDSTDBY => OPEN);
-- System Clock Multiplied
OSCmain: MASTERCLOCK
PORT MAP (CLKI => INTERNAL_CLOCK, CLKOP => CLOCK, CLKOS => CLOCK_65);
-- Gets data from ONE ADC
ADCIn: InputBuffer
GENERIC MAP (n => DATAWIDTH)
PORT MAP( clk => CLOCK, CLK65 =>CLOCK_65, EN =>'0', Ipin => adcInPut, Output => OUTPUT, STRT => ADC_SRT );
adcInPut <= ADCInputBuffer;
end ADReader;
InputBuffer:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity InputBuffer is
generic(n: natural :=4 );
Port (
clk : in STD_LOGIC;
CLK65 : IN STD_LOGIC;
En : in STD_LOGIC;
STRT : OUT STD_LOGIC;
Ipin : in STD_LOGIC_VECTOR (n-1 downto 0);
Output : out STD_LOGIC_VECTOR (n-1 downto 0)
);
end InputBuffer;
architecture Behavioral of InputBuffer is
signal temp : STD_LOGIC_VECTOR(n-1 downto 0);
SIGNAL CLK2 : STD_LOGIC;
begin
-- invert the signal from the push button switch and route it to the LED
process(clk, En)
begin
if( En = '1') then
temp <= B"0000";
elsif rising_edge(clk) then
temp <= Ipin;
end if;
end process;
Output <= temp;
STRT <= CLK65;
end Behavioral;
this is the setting for MASTERCLOCK generated by lattice diamond:
this is how the pins are setup:
and here is the netlist generated by lattice-diamond:
here I'm just trying to have a static output:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TOP is
GENERIC(
DATAWIDTH : natural := 4
);
PORT(
OUTPUT : OUT STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0)
);
end TOP;
architecture ADReader of TOP is
begin
OUTPUT <= B"1010";
end ADReader;
Page 15 of the user guide (The link you provided) mentions different LED pins: H11,J13,J11,L12 which you have as ADC input. I think you might have swapped some pins around...

Pseudo Random Number Generator using LFSR in VHDL

I'm having a bit of trouble creating a prng using the lfsr method. Here is my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pseudorng is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0);
check: out STD_LOGIC);
constant seed: STD_LOGIC_VECTOR(7 downto 0) := "00000001";
end pseudorng;
architecture Behavioral of pseudorng is
signal temp: STD_LOGIC;
signal Qt: STD_LOGIC_VECTOR(7 downto 0);
begin
PROCESS(clock)
BEGIN
IF rising_edge(clock) THEN
IF (reset='1') THEN Qt <= "00000000";
ELSE Qt <= seed;
END IF;
temp <= Qt(4) XOR Qt(3) XOR Qt(2) XOR Qt(0);
--Qt <= temp & Qt(7 downto 1);
END IF;
END PROCESS;
check <= temp;
Q <= Qt;
end Behavioral;
Here is the simulation I have ran:
prng sim
Firstly, the check output is just there so I can monitor the output of the temp signal. Secondly, the line that is commented out is what is causing the problem.
As can be seen from the simulation, on the first rising edge of the clock, the Qt signal reads the seed. However, and this is my question, for some reason the temp signal only XORs the bits of the Qt signal on the second rising edge of the clock. It remains undefined on the first clock pulse. Why is that? If it operated on the first rising edge right after the Qt signal reads the seed, then I could uncomment the line that shifts the bits and it would solve my problem. Any help would be much appreciated!
Here is the test bench if anyone cares:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_pseudorng is
end tb_pseudorng;
architecture bench of tb_pseudorng is
COMPONENT pseudorng
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0);
check: out STD_LOGIC);
END COMPONENT;
signal clock1: STD_LOGIC;
signal reset1: STD_LOGIC;
signal Q1: STD_LOGIC_VECTOR(7 downto 0);
signal check1: STD_LOGIC;
begin
mapping: pseudorng PORT MAP(
clock => clock1,
reset => reset1,
Q => Q1,
check => check1);
clock: PROCESS
BEGIN
clock1<='0'; wait for 50ns;
clock1<='1'; wait for 50ns;
END PROCESS;
reset: PROCESS
BEGIN
reset1<='0'; wait for 900ns;
END PROCESS;
end bench;
I made some slight modifications to what you had (you are pretty much there though); I don't think the LFSR would step properly otherwise. I added an enable signal to the LFSR so you can effectively control when you want it to step. Resulting sim is here.
Just as a sidenote, you could also include a load and seed inputs if you wanted to seed the LFSR with a different value (instead of making it const).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pseudorng is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
en : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0);
check: out STD_LOGIC);
-- constant seed: STD_LOGIC_VECTOR(7 downto 0) := "00000001";
end pseudorng;
architecture Behavioral of pseudorng is
--signal temp: STD_LOGIC;
signal Qt: STD_LOGIC_VECTOR(7 downto 0) := x"01";
begin
PROCESS(clock)
variable tmp : STD_LOGIC := '0';
BEGIN
IF rising_edge(clock) THEN
IF (reset='1') THEN
-- credit to QuantumRipple for pointing out that this should not
-- be reset to all 0's, as you will enter an invalid state
Qt <= x"01";
--ELSE Qt <= seed;
ELSIF en = '1' THEN
tmp := Qt(4) XOR Qt(3) XOR Qt(2) XOR Qt(0);
Qt <= tmp & Qt(7 downto 1);
END IF;
END IF;
END PROCESS;
-- check <= temp;
check <= Qt(7);
Q <= Qt;
end Behavioral;
And tb:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_pseudorng is
end tb_pseudorng;
architecture bench of tb_pseudorng is
COMPONENT pseudorng
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
en : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0);
check: out STD_LOGIC);
END COMPONENT;
signal clock1: STD_LOGIC;
signal reset1: STD_LOGIC;
signal Q1: STD_LOGIC_VECTOR(7 downto 0);
signal check1: STD_LOGIC;
signal en : STD_LOGIC;
begin
mapping: pseudorng PORT MAP(
clock => clock1,
reset => reset1,
en => en,
Q => Q1,
check => check1);
clock: PROCESS
BEGIN
clock1 <= '0'; wait for 50 ns;
clock1 <= '1'; wait for 50 ns;
END PROCESS;
reset: PROCESS
BEGIN
reset1 <= '0';
en <= '1';
wait for 900 ns;
END PROCESS;
end bench;

Place:1108 error in VHDL (Help)

I am designing a simple combination lock design in VHDL on a Spartan 6 FPGA. This error has come up and i am a bit confused to how i could fix it. I have "googled" this and according to this answer in this thread Too many comps of type “BUFGMUX” found to fit this deviceI beleive i know the problem but i am unsure how to solve it.
Now correct me if i am wrong but i believe this error came about due to the following code in my design
--clock divider
process(cclk,clr)
begin
if (clr ='1') then
Count200Hz <= X"00000";
--clk200 <= '0';
temp <= '0';
elsif rising_edge(cclk) then
if (Count200Hz = clk200HzEndVal) then
clk200 <= not temp;
Count200Hz <= X"00000";
else
Count200Hz <= Count200Hz + '1';
end if;
end if;
end process;
-- 2-bit counter
process(cclk,clr)
begin
if clr = '1' then
s <= "00";
elsif rising_edge(cclk) then
s <= s+1;
end if;
end process;
--state machine
state_mach:PROCESS(lclk, clr)
BEGIN
IF clr = '1' THEN
present_state <= idle;
ELSIF rising_edge(lclk) THEN
present_state <= next_state;
end if;
END PROCESS;
pulse_process: process(cclk, rst)
begin
if rst = '0' then
pulse <= '0';
count <= 0;
current_state <= idle;
elsif (rising_edge(cclk))then
current_state <= next_state;
....
These code are from different vhdl modules in my design.
does the ise believes that there are three different clock used in my design hence why the error is thrown??
The thing is that they are different clock but they stem from the systems clock ones the clock at an lower frequency, one is the clock pulse.
I have added my top-level design for some clarity
Any help is appreciated
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity simpleLock_top is
Port (
mclk : in STD_LOGIC;
rst : in STD_LOGIC;
btnl : in STD_LOGIC;
btnr : in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (3 downto 0);
seg7 : out STD_LOGIC_VECTOR (6 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC_VECTOR (7 DOWNTO 0);
dp : out STD_LOGIC);
end simpleLock_top;
architecture Behavioral of simpleLock_top is
component x7seg_msg is
Port (
x : in STD_LOGIC_VECTOR (15 downto 0);
cclk : in STD_LOGIC;
clr : in STD_LOGIC;
seg7 : out STD_LOGIC_VECTOR (6 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0);
dp : out STD_LOGIC);
end component;
component clkdiv is
Port (
cclk : in STD_LOGIC;
clr : in STD_LOGIC;
clk200 : out STD_LOGIC);
end component;
component simpleLock is
PORT (
lclk : IN STD_LOGIC;
clr : IN STD_LOGIC;
btnl : IN STD_LOGIC;
btnr : IN STD_LOGIC;
code : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
led : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
digit : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
user_input : OUT STD_LOGIC_VECTOR(15 downto 0));
end component;
component clock_pulse is
PORT (
cclk : IN STD_LOGIC;
rst : IN STD_LOGIC;
trig : IN STD_LOGIC;
pulse : OUT STD_LOGIC);
end component;
constant code : STD_LOGIC_VECTOR(15 downto 0):= X"1234";
signal digit: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal user_input : std_logic_vector(15 downto 0);
signal clk200, clkp, btn01: STD_LOGIC;
signal btn : STD_LOGIC_VECTOR(1 DOWNTO 0);
begin
btn(0) <= btnr;
btn(1) <= btnl;
btn01 <= btn(0) or btn(1);
--led <= X"00";
V1: clkdiv
port map(
cclk => mclk,
clr => rst,
clk200 => clk200);
V2: x7seg_msg
port map(
x => user_input,
cclk => clk200,
clr => rst,
seg7 => seg7,
an => an,
dp => dp );
V3: simpleLock
port map(
lclk => clkp,
clr => rst,
btnl => btnl,
btnr => btnr,
code => code,
sw => sw,
led => led,
digit => digit,
user_input => user_input);
V4: clock_pulse
port map(
cclk => clk200,
rst => rst,
trig => btn01,
pulse => clkp);
end Behavioral;
Clock Enable
In an FPGA design, it is often better to use the less possible different clocks.
If your "clock_pulse" module generate a one cycle clock pulse, don't use this pulse as a clock ('clkp' in your code), but as a clock enable ('enable' in the code below).
myproc : process(clk, rst)
begin
if rst = '1' THEN
-- your asynchronously reseted signals
elsif rising_edge(clk) THEN
if enable = '1' then
-- things that must be done when you get the one cycle pulse
end if;
end if;
end process;
But take care of any unmanaged clock domain crossing...
Hope this helps.

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