I've got multiple (same) input/output to declare :
B1_data_to_send : in std_logic_vector(15 downto 0);
B1_start_transmission : out std_logic;
B1_transmission_busy : in std_logic;
B2_data_to_send : in std_logic_vector(15 downto 0);
B2_start_transmission : out std_logic;
B2_transmission_busy : in std_logic;
B3_data_to_send : in std_logic_vector(15 downto 0);
B3_start_transmission : out std_logic;
B3_transmission_busy : in std_logic;
B4_data_to_send : in std_logic_vector(15 downto 0);
B4_start_transmission : out std_logic;
B4_transmission_busy : in std_logic;
B5_data_to_send : in std_logic_vector(15 downto 0);
B5_start_transmission : out std_logic;
B5_transmission_busy : in std_logic;
B6_data_to_send : in std_logic_vector(15 downto 0);
B6_start_transmission : out std_logic;
B6_transmission_busy : in std_logic;
I've got 30 block like this to create, is there a way to avoid this repetition and to create a generic block that I can instantiate with different names ?
Arrays are what you need here. First, you will need to create an array type of std_logic_vector in a package. If you're using VHDL 2008, it can simply be an unconstrained type:
package types_pkg is
type slv_array_t is array(natural range <>) of std_logic_vector;
end package;
and then use this type in your entity:
use work.types_pkg.all;
entity your_entity is
port (
B_data_to_send : in slv_array_t (1 to 30)(15 downto 0);
B_start_transmission : out std_logic_vector(1 to 30);
B_transmission_busy : in std_logic_vector(1 to 30)
);
end entity;
Of course, any of the dimensions can come from a generic.
use work.types_pkg.all;
entity your_entity is
generic (
G_N_PORTS : natural;
G_D_WIDTH : natural
);
port (
B_data_to_send : in slv_array_t (0 to G_N_PORTS-1)(G_D_WIDTH-1 downto 0);
B_start_transmission : out std_logic_vector(0 to G_N_PORTS-1);
B_transmission_busy : in std_logic_vector(0 to G_N_PORTS-1)
);
end entity;
I want to use records as I have multiple ports which at the same time are composed by multiple signals. The issue is that some signals are in and some are out (AXI stream, specifically).
I want to avoid doing this:
port (
s0_axis_tvalid : in STD_LOGIC;
s0_axis_tdata : in STD_LOGIC_VECTOR (Data_Width-1 downto 0);
s0_axis_tlast : in STD_LOGIC;
s0_axis_tready : out STD_LOGIC;
s1_axis_tvalid : in STD_LOGIC;
s1_axis_tdata : in STD_LOGIC_VECTOR (Data_Width-1 downto 0);
s1_axis_tlast : in STD_LOGIC;
s1_axis_tready : out STD_LOGIC;
m0_axis_tvalid : out STD_LOGIC;
m0_axis_tdata : out STD_LOGIC_VECTOR (Data_Width-1 downto 0);
m0_axis_tlast : out STD_LOGIC;
m0_axis_tready : in STD_LOGIC);
So, I want to have some records looking like this:
type AXIS_Slave is record
s_axis_tvalid : STD_LOGIC;
s_axis_tdata : STD_LOGIC_VECTOR (Data_Width-1 downto 0);
s_axis_tlast : STD_LOGIC;
s_axis_tready : STD_LOGIC;
end record AXIS_Slave;
type AXIS_Master is record
s_axis_tvalid : STD_LOGIC;
s_axis_tdata : STD_LOGIC_VECTOR (Data_Width-1 downto 0);
s_axis_tlast : STD_LOGIC;
s_axis_tready : STD_LOGIC;
end record AXIS_Master;
Now, the port in my TOP's entity design should be:
Port (
s0: AXIS_Slave;
s1: AXIS_Slave;
m0: AXIS_Master);
The problem is that I need to declare in the Port whether it is in or out but the direction of each signal should be defined in the record, which I believe is not allowed as I get a warning "Syntax error near in" or "Syntax error near out".
So, how can I declare a type which has in and out signals?
I want to write an IP to store/read data using BRAM.
What I have so far is using the (C)DMA to read memory mapped data out of the RAM and get an AXIS.
Then I created a new source file in VHDL to accept the AXIS on one side which worked like a charm.
On the other side I want to create a BRAM interface but vivado does not combine ports for the BRAM interface.
Located in the "vivado/data/ip/interfaces/bram_v1_0" folder a file "bram_rtl.xml" is present.
I tried to use the ports used in the xml file.
Especially the ports with the "required" tag.
The AXI BRAM Controller is combining them right so I am pretty sure I made a mistake. Using the same naming like the AXI BRAM Controller didn't work either.
My VHDL looks like this:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AXIS_TO_BRAM is
generic (
addr_size : integer range 1 to 12 := 10
);
Port (
--axistream
tdata : in std_logic_vector(31 downto 0);
tkeep : in std_logic_vector(3 downto 0);
tlast : in std_logic;
tready : out std_logic;
tvalid : in std_logic;
aclk : in std_logic;
--BRAM
en : out std_logic;
dout : in std_logic_vector(31 downto 0);
din : out std_logic_vector(31 downto 0);
we : out std_logic;
addr : out std_logic_vector(addr_size-1 downto 0);
clk : out std_logic;
rst : out std_logic);
end AXIS_TO_BRAM;
architecture Behavioral of AXIS_TO_BRAM is
begin
end Behavioral;
I am using vivado 2016.4 for Zynq 7020 on Linux.
Is there something missing in the VHDL code to get vivado recognize my ports as BRAM interface or is this a bug in this version?
Thank your for any ideas
Here is the complete working and synthesizable VHDL code.
The correct solution (or at least the important part) is given in the comments by Vinay Madapura.
The predefined interfaces can be found in the folder $vivado/$version/data/ip/interfaces.
I hope this code will help other people struggling with similar problems.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AXIS_TO_BRAM is
generic(
addr_size : integer range 1 to 12 := 10
);
Port(
tdata : in std_logic_vector(31 downto 0);
tkeep : in std_logic_vector(3 downto 0);
tlast : in std_logic;
tready : out std_logic;
tvalid : in std_logic;
aclk : in std_logic;
addra : out std_logic_vector(addr_size-1 downto 0);
clka : out std_logic;
dina : out std_logic_vector(31 downto 0);
douta : in std_logic_vector(31 downto 0);
ena : out std_logic;
rsta : out std_logic;
wea : out std_logic_vector(0 downto 0)
);
end AXIS_TO_BRAM;
architecture Behavioral of AXIS_TO_BRAM is
ATTRIBUTE X_INTERFACE_INFO : string;
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
begin
end Behavioral;
I have a problem with my program in xilinx vhd.
I have to create a processor that supports the classic instructions of MIPS32
add, sub, and, or, lw, sw, sine and cosine. Sine and Cosine will take as argument a number and will return the cos or sin of the angle in ΙΕΕΕ-754 Single precision and Integer from 0 – 1000.
I have an excel file which produce a hex output(for the commands of Mips32) that i use in one components(in InstructionRom)
The input numbers that I want to add or sub or and ..etc..I write them in HEX in the component DataRam.
The problem is with the top component in ReadData1 and ReadData2 I got the same values.
Below I have 2 screenshots and how the top entity is connected with other components.
Other components are working.
Can anyone take a look please?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity myTOP is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
instruction : out STD_LOGIC_VECTOR (31 downto 0);
regA : out STD_LOGIC_VECTOR (31 downto 0);
regB : out STD_LOGIC_VECTOR (31 downto 0);
ALUout : out STD_LOGIC_VECTOR (31 downto 0);
writeReg : out STD_LOGIC_VECTOR (4 downto 0);
Opcode : out STD_LOGIC_VECTOR (5 downto 0);
SinCos : out STD_LOGIC_VECTOR (31 downto 0);
DataOUT : out STD_LOGIC_VECTOR (31 downto 0);
ReadDATA1 : out STD_LOGIC_VECTOR (31 downto 0);
ReadDATA2 : out STD_LOGIC_VECTOR (31 downto 0);
WriteData : out STD_LOGIC_VECTOR (31 downto 0));
end myTOP;
architecture Behavioral of myTOP is
component InstructionsROM is
Port ( InstructionAddress : in STD_LOGIC_VECTOR (9 downto 0);
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component myPCRegister is
Port ( PC_INPUT : in STD_LOGIC_VECTOR (9 downto 0);
PC_OUTPUT : out STD_LOGIC_VECTOR (9 downto 0);
clk : in STD_LOGIC;
RESET : in STD_LOGIC);
end component;
component my_10bitAdder is
Port ( a : in STD_LOGIC_VECTOR (9 downto 0);
b : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
z : out STD_LOGIC_VECTOR (9 downto 0));
end component;
component my_5bitMUX is
Port ( a : in STD_LOGIC_VECTOR (4 downto 0);
b : in STD_LOGIC_VECTOR (4 downto 0);
s : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (4 downto 0));
end component;
component my32to9bit is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
z : out STD_LOGIC_VECTOR (8 downto 0));
end component;
component my32BitRegistersFile is
Port ( ReadRegister1 : in STD_LOGIC_VECTOR (4 downto 0);
ReadRegister2 : in STD_LOGIC_VECTOR (4 downto 0);
WriteRegister : in STD_LOGIC_VECTOR (4 downto 0);
WriteData : in STD_LOGIC_VECTOR (31 downto 0);
ReadData1 : out STD_LOGIC_VECTOR (31 downto 0);
ReadData2 : out STD_LOGIC_VECTOR (31 downto 0);
ReadData3 : out STD_LOGIC_VECTOR (31 downto 0);
RegWrite : in STD_LOGIC;
clk : in STD_LOGIC;
Reset : in STD_LOGIC);
end component;
component myControlUnit is
Port ( A : in STD_LOGIC_VECTOR (5 downto 0);
RegDst : out STD_LOGIC;
ALUSrc : out STD_LOGIC;
MemtoReg : out STD_LOGIC;
RegWrite : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
ALUop1 : out STD_LOGIC;
SinCos : out STD_LOGIC;
FI : out STD_LOGIC);
end component;
component my16to32bit is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
z : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component myALUControl is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
s : in STD_LOGIC;
op1 : out STD_LOGIC;
op2 : out STD_LOGIC;
bin : out STD_LOGIC);
end component;
component myALU_32bit is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
b : in STD_LOGIC_VECTOR (31 downto 0);
bin : in STD_LOGIC;
cin : in STD_LOGIC;
op1 : in STD_LOGIC;
op2 : in STD_LOGIC;
cout : out STD_LOGIC;
z : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component my_SinCos is
Port ( I1 : in STD_LOGIC_VECTOR (8 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
e : out STD_LOGIC;
O : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component DataRAM is
Port ( DataAddress : in STD_LOGIC_VECTOR (9 downto 0);
clk : in STD_LOGIC;
readData : in STD_LOGIC;
writeData : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR (31 downto 0);
DataOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component my_32bitMUX is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
b : in STD_LOGIC_VECTOR (31 downto 0);
s : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal S2, S4, S5, S6, S7, S9 , S10 , S11, S12, S13, S14, S15, S16, S17 : STD_LOGIC_VECTOR(31 downto 0);
signal S0, S1:STD_LOGIC_VECTOR (9 downto 0);
signal S3:STD_LOGIC_VECTOR (4 downto 0);
signal S8:STD_LOGIC_VECTOR (8 downto 0);
signal SC:STD_LOGIC_VECTOR (8 downto 0);
signal SA :STD_LOGIC_VECTOR (2 downto 0);
signal S18:STD_LOGIC;
begin
U0: myPCRegister port map(PC_INPUT=>S1, PC_OUTPUT=>S0, clk=>clk, RESET=>reset);
U1: my_10bitAdder port map (a=>S0, b=>'1', cin=>'0', z=>S1);
U2: InstructionsROM port map(InstructionAddress=>S0 , Instruction=> S2 );
U3: my_5bitMUX port map( a=> S2(15 downto 11), b=>S2(20 downto 16), s=>SC(0), z=>S3);
U4: my32BitRegistersFile port map(ReadRegister1=>S2(25 downto 21), ReadRegister2=>S2(20 downto 16), WriteRegister=>S3, WriteData=>S17, ReadData1=>S5, ReadData2=>S6, RegWrite=>SC(3), clk=>clk, Reset=>reset );
U5: myControlUnit port map(A=>S2(31 downto 26),RegDst=>SC(0), ALUSrc=>SC(1), MemtoReg=>SC(2), RegWrite=>SC(3), MemRead=>SC(4), MemWrite=>SC(5), ALUop1=>SC(6), SinCos=>SC(7), FI=>SC(8));
U6: my16to32bit port map(a=>S2, z=>S4);
U7: myALUControl port map(a=>S2(2 downto 0), s=>SC(6),bin=>SA(0), op1=>SA(1), op2=>SA(2));
U8: my_32bitMUX port map(a=>S4, b=>S6, s=>SC(1), z=>S10);
U9: my_32bitMUX port map(a=>S11, b=>S5, s=>SC(8), z=>S9);
U10: myALU_32bit port map(a=>S9, b=>S10, cin=>'0', bin=>SA(0), op1=>SA(1), op2=>SA(2), z=>S12);
U11: my_32bitMUX port map(a=> S5, b=>S12, s=>SC(8), z=>S7);
U12: my32to9bit port map(a=>S7, z=>S8);
U13: my_SinCos port map(I1=>S8, s=>S2(31 downto 30), e=>S18, O=>S11);
U14: DataRAM port map(DataAddress=>S2(9 downto 0), clk=>clk, readData=>SC(4), writeData=>SC(5), DataIn=>S6, DataOut=>S14);
U15: my_32bitMUX port map(a=>S12, b=>S11, s=>SC(8), z=>S13);
U16: my_32bitMUX port map(a=>S14, b=>S12, s=>SC(2), z=>S15);
U17: my_32bitMUX port map(a=>S11, b=>S15, s=>SC(7), z=>S16);
U18: my_32bitMUX port map(a=>S11, b=>S16, s=>S18, z=>S17);
instruction<=S2;
regA<=S9;
regB<=S10;
ALUout<=S12;
writeReg<=S3;
Opcode<=S2(31 downto 26);
SinCos<= S11;
DataOUT<=S14;
WriteData<=S17;
ReadDATA1<= S5;
ReadDATA2 <=S6;
end Behavioral;
DATARAM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DataRAM is
Port ( DataAddress : in STD_LOGIC_VECTOR (9 downto 0);
clk : in STD_LOGIC;
readData : in STD_LOGIC;
writeData : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR (31 downto 0);
DataOut : out STD_LOGIC_VECTOR (31 downto 0));
end DataRAM;
architecture Behavioral of DataRAM is
-- Define a new type with the name RAM_Array of 8 bits
type RAM_Array is array (0 to 1023)
of std_logic_vector(7 downto 0);
-- Set some initial values in RAM for Testing
signal RAMContent: RAM_Array := (
0 => X"0A", 1 => X"00", 2 => X"00", 3 => X"00",
4 => X"05", 5 => X"00", 6 => X"00", 7 => X"00",
8 => X"2C", 9 => X"01", 10 => X"00", 11 => X"00",
12 => X"00", 13 => X"00", 14 => X"00", 15 => X"00",
others => X"00");
begin
-- This process is called when we READ from RAM
p1: process (readData, DataAddress)
begin
if readData = '1' then
DataOut(7 downto 0) <= RAMContent(conv_integer(DataAddress));
DataOut(15 downto 8) <= RAMContent(conv_integer(DataAddress+1));
DataOut(23 downto 16) <= RAMContent(conv_integer(DataAddress+2));
DataOut(31 downto 24) <= RAMContent(conv_integer(DataAddress+3));
else
DataOut <= (DataOut'range => 'Z');
end if;
end process;
-- This process is called when we WRITE into RAM
p2: process (clk, writeData)
begin
if (clk'event and clk = '1') then
if writeData ='1' then
RAMContent(conv_integer(DataAddress)) <= DataIn(7 downto 0);
RAMContent(conv_integer(DataAddress+1)) <= DataIn(15 downto 8);
RAMContent(conv_integer(DataAddress+2)) <= DataIn(23 downto 16);
RAMContent(conv_integer(DataAddress+3)) <= DataIn(31 downto 24);
end if;
end if;
end process;
end Behavioral;
INSTRUCTION ROM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InstructionsROM is
Port ( InstructionAddress : in STD_LOGIC_VECTOR (9 downto 0);
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end InstructionsROM;
architecture Behavioral of InstructionsROM is
-- Define a new type with the name ROM_Array of 32 bits
type ROM_Array is array (0 to 1024)
of std_logic_vector(31 downto 0);
-- The data here should be replaced with the intructions in HEX
constant ROMContent: ROM_Array := (
X"8C000000",
X"8C810000",
X"00201822",
X"00201824",
X"00201825",
X"8D000000",
X"8D810000",
X"BC03000A",
X"FC03000A",
X"3C03000A",
X"7C03000A",
others => X"00000000");
begin
Instruction <= ROMContent(conv_integer(InstructionAddress));
end Behavioral;
DataRam and instructionrom were given to us ready ..we just change the values (it depends on what instruction we want to do)
Here are some serious problems with your code:
P1: process sensitivity list should include RAMContent
U1: cout is not connected
U4: readdata3 is not connected
U10: cout is not connected
U14: component my_32bitMUX_937286 is not declared. This gives a compilation error
The first four problems can cause problems without warnings from your simulator. The last is an error and would normally cause your simulator to throw and error and refuse to start the simulation.
When I try to compile this code I keep getting an error that says:
line 13: Error, 'std_logic' is not a known type.
Line 13 is Clock : IN std_logic;in the ALU_tb entity.
I am confused by this error, because it is my understanding that the reason for said error is normally a missing library/package. I'm almost sure I have the appropriate libraries and packages. Plus none of the other signals of type std_logic are getting errors.
If anyone could help me figure this out, I would greatly appreciate it.
-- VHDL Entity ALU.ALU_tb.symbol
--
-- Created:
-- by - ClarkG.UNKNOWN (COELABS15)
-- at - 19:58:20 09/ 8/2014
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2011.1 (Build 18)
--
ENTITY ALU_tb IS
PORT(
Clock : IN std_logic;
Reset_N : IN std_logic
);
-- Declarations
END ALU_tb ;
--
-- VHDL Architecture ALU.ALU_tb.struct
--
-- Created:
-- by - ClarkG.UNKNOWN (COELABS15)
-- at - 19:58:20 09/ 8/2014
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2011.1 (Build 18)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
LIBRARY ALU;
ARCHITECTURE struct OF ALU_tb IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL A : std_logic_vector(31 DOWNTO 0);
SIGNAL ALUOp : std_logic_vector(3 DOWNTO 0);
SIGNAL B : std_logic_vector(31 DOWNTO 0);
SIGNAL Overflow : std_logic;
SIGNAL R : std_logic_vector(31 DOWNTO 0);
SIGNAL SHAMT : std_logic_vector(4 DOWNTO 0);
SIGNAL Zero : std_logic;
-- Component Declarations
COMPONENT ALU
PORT (
A : IN std_logic_vector (31 DOWNTO 0);
ALUOp : IN std_logic_vector (3 DOWNTO 0);
B : IN std_logic_vector (31 DOWNTO 0);
SHAMT : IN std_logic_vector (4 DOWNTO 0);
Overflow : OUT std_logic ;
R : OUT std_logic_vector (31 DOWNTO 0);
Zero : OUT std_logic
);
END COMPONENT;
COMPONENT ALU_tester
PORT (
A : IN std_logic_vector (31 DOWNTO 0);
ALUOp : IN std_logic_vector (3 DOWNTO 0);
B : IN std_logic_vector (31 DOWNTO 0);
Clock : IN std_logic ;
Overflow : IN std_logic ;
R : IN std_logic_vector (31 DOWNTO 0);
Reset_N : IN std_logic ;
SHAMT : IN std_logic_vector (4 DOWNTO 0);
Zero : IN std_logic
);
END COMPONENT;
COMPONENT Test_transaction_generator
PORT (
Clock : IN std_logic ;
A : OUT std_logic_vector (31 DOWNTO 0);
ALUOp : OUT std_logic_vector (3 DOWNTO 0);
B : OUT std_logic_vector (31 DOWNTO 0);
SHAMT : OUT std_logic_vector (4 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : ALU USE ENTITY ALU.ALU;
FOR ALL : ALU_tester USE ENTITY ALU.ALU_tester;
FOR ALL : Test_transaction_generator USE ENTITY ALU.Test_transaction_generator;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
U_0 : ALU
PORT MAP (
A => A,
ALUOp => ALUOp,
B => B,
SHAMT => SHAMT,
Overflow => Overflow,
R => R,
Zero => Zero
);
U_1 : ALU_tester
PORT MAP (
A => A,
ALUOp => ALUOp,
B => B,
Clock => Clock,
Overflow => Overflow,
R => R,
Reset_N => Reset_N,
SHAMT => SHAMT,
Zero => Zero
);
U_2 : Test_transaction_generator
PORT MAP (
Clock => Clock,
A => A,
ALUOp => ALUOp,
B => B,
SHAMT => SHAMT
);
END struct;
The context clause comprised of a library clauses and use clauses should be moved to before the entity declaration instead of just before the architecture body. An entity and an architecture form a common declarative region allowing those library and use clauses to be in effect across both instead of just the architecture, as in your code presently.
You also don't appear to be using package std_logic_arith in the code you've shown. (The architecture only contains components).
At line 13, you have not yet imported the ieee libraries required to define std_logic which is why you're getting the error.