Testbench for a reaction timer design VHDL - vhdl

Question

I have to test using modelsim this component:
COMPONENT part5
PORT ( CLOCK_50,KEY0,KEY3 : IN STD_LOGIC;
SW: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
HEX3,HEX2,HEX1,HEX0: OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
It will be implemented on altera DE2.
It is supposed to work with the clock (CLOCK_50),after KEY0 goes to logic level 1, counting clock periods till it reach the numeber inserted on SW(7 DOWNTO 0),at this point it turns on a red led : LEDR. From the time LEDR is ON the four hexadecimal displays (HEX0, HEX1,HEX2 and HEX3) start to count at 1 ms interval. I have to push a button KEY3 (on the DE2 board) as quickly as possible till I reach the value rappresented in SW(7 DOWNTO 0) : the red light turns off and displays stop counting.
I tried with this:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;`
ENTITY tb_part5 IS
END ENTITY;
ARCHITECTURE beha OF tb_part5 IS
COMPONENT part5
PORT ( CLOCK_50,KEY0,KEY3 : IN STD_LOGIC;
SW: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
HEX3,HEX2,HEX1,HEX0: OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
SIGNAL clk,key,rst: STD_LOGIC:='0';--inputs
SIGNAL switch: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL led,led1: STD_LOGIC;--outputs
SIGNAL dec0,dec1,dec2,dec3 : STD_LOGIC_VECTOR (6 DOWNTO 0);
BEGIN
switch<="00001010";
PROCESS --clock
BEGIN
clk<='1' AFTER 10 ns ;
clk<='0' AFTER 20 ns ;
END PROCESS;
PROCESS --reset
BEGIN
rst<='0';
WAIT FOR 20 ns;
rst<='1';
WAIT;
END PROCESS;
PROCESS
BEGIN
IF led='1' THEN
key<= '1';
WAIT FOR 20 ns;
key<='0';
WAIT FOR 20 ns;
ELSE
key<='0';
END IF;
END PROCESS;
DUT : part5 PORT MAP (CLOCK_50=>clk, KEY0=>rst,KEY3=>key,SW=>switch,HEX3=>dec3,HEX2=>dec2,HEX1=>dec1,HEX0=>dec0,LEDR(0)=>led,LEDR(1)=>led1);
END beha;
But the simulation don't show any results. I'm not very good at testbenches, I really want to understand how they works, specially with the generation of the clock, and insertion of wave vectors! Maybe I've could explain my doubts better, but if someone could show me a testbench example for beginners it would be very helpful!
Thanks

Answer 1

A beginners architecture for test bench can be really simple. You can test a lot of components with just 5 process (including clk and reset process). When you create a test bench you will usually generate at least one clock and a reset for your design under test (DUT). For those process you can keep the following and this should work for all single clock design (does not matter if reset is synchronous or asynchronous). Then you will create a stimulus process. This process will allow you to generate data for your DUT (you will affect signals connected to your DUT). This process can define the end of your simulation. You can set some signals and wait for 100000 ns if you want to test a sequence without modify signals (DUT inputs).
After generate stimulus you can launch simulation and manually verify your DUT outputs but this in not the best way to do (maybe in your case but not in a bigger design). The easiest way to control the integrity of your outputs is to generate a reference. This reference is the expected reaction of your design. E.g : if you want to realize a design that wait 100 clock cycles. You will create a reference signal of the output but you do not have to use VHDL that you can synthesize. You have access to all VHDL function (wait for, wait until, etc...).
At the end you will have the last process, the checker. This one will compare dut outputs and reference to define if there is some errors or not in your design.
Do not forget to put a wait statement in all process (depending on end_sim_s per exemple) to stop your simulation when everthing has been simulated
Here is an empty test bench structure :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_part5 is
port (
-- no IO for test bench
);
end entity;
architecture beha of tb_part5 is
---------------
-- Constants --
---------------
constant CLOCK_PERIOD : time := 10 ns; -- e.g.
------------------------
-- Test bench signals --
------------------------
signal clk_sti : std_logic := '0';
signal rst_sti : std_logic := '1'; -- !!! activ high !!!
-- end of sim flag
signal end_sim_s : boolean := false;
begin
----------------------
-- Clock generation --
----------------------
process
begin
clk_sti <= '1';
wait for CLOCK_PERIOD/2;
clk_sti <= '0';
wait for CLOCK_PERIOD/2;
if end_sim_s = true then
wait; -- end of simulation
end if;
end process;
--------------------
-- Reset sequence --
--------------------
process
begin
rst <= '1';
wait for 2*CLOCK_PERIOD;
rst <= '0';
wait;
end process;
----------------------
-- Stimulus process --
----------------------
process
begin
-- default values for DUT inputs
-- wait end of reset sequence
wait until (rst_sti = '0');
-- do something
-- end of simulation
end_sim_s <= true;
wait;
end process;
-----------------------
-- Reference process --
-----------------------
-------------------
-- Check process --
-------------------
-----------------------
-- DUT instanciation --
-----------------------
end beha;
For your test bench I propose you the following architecture. But you have to be conscious your test bench does not verify anything.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_part5 is
port (
-- no IO in test bench
);
end entity;
architecture beha of tb_part5 is
---------------
-- Constants --
---------------
constant CLOCK_PERIOD : time := 10 ns; -- e.g.
-----------------------
-- Internals signals --
-----------------------
signal clk, key, rst : std_logic := '0'; --inputs
signal switch : std_logic_vector (7 downto 0);
signal led, led1 : std_logic; --outputs
signal dec0, dec1, dec2, dec3 : std_logic_vector (6 downto 0);
-- test bench signals
signal end_sim_s : boolean := false;
begin
switch <= "00001010";
----------------------
-- Clock generation --
----------------------
process
begin
clk <= '0';
wait for CLOCK_PERIOD/2;
clk <= '1';
wait for CLOCK_PERIOD/2;
if end_sim_s = true then
wait; -- end of simulation
end if;
end process;
--------------------
-- Reset sequence --
--------------------
process
begin
-- TIPS : if you want to be more efficient you should us a norm to
-- define your signal. A reset signal activ low can be called nRst for
-- exemple. Maybe actually you have an activ low reset but maybe not.
-- This exemple show a reset activ low sequence
rst <= '0';
wait for 2*CLOCK_PERIOD;
rst <= '1';
wait;
end process;
---------------------
-- Your TEST bench --
---------------------
-- this part do the same thing that you were asking.
process
begin
-- the if statement in the previous version is not a good thing to do.
-- in fact, you want your process to wait until an event.
-- initial state (default value)
key <= '0';
-- wait until the end of reset sequence (just in case)
wait until (rst = '1'); -- e.g.
-- wait until DUT assert led
wait until (led = '1'); -- e.g.
-- start your sequence
key <= '1';
wait for 20 ns;
key <= '0';
wait for 20 ns;
-- here you have 2 choices. let the process iterate a second time or just
-- end the simulation at this moment
-- stop here
-- notify the others process the end of simulation
end_sim_s <= true;
-- block process
wait;
end process;
-----------------------
-- DUT instanciation --
-----------------------
DUT : part5 port map (
CLOCK_50 => clk,
KEY0 => rst,
KEY3 => key,
SW => switch,
HEX3 => dec3,
HEX2 => dec2,
HEX1 => dec1,
HEX0 => dec0,
LEDR(0) => led,
LEDR(1) => led1
);
end beha;
Hope this will help you.
Regards.
Mike