Entity has no architecture problem in Modelsim - vhdl

Question

I'm new to FPGA design using VHDL and I'm stucked in a problem of testbench simulation: each time I try to simulate my model (which testbench was given by the testbench writer) I get the following error that's driving me crazy:
Error: (vsim-3173) Entity >'C:/intelFPGA_lite/progetto_dsp/simulation/modelsim/rtl_work.progetto_dsp_top_vhd_t>st' has no architecture.
My model is a simple Phase Frequency Detector (PFD) and all I'd like is to simulate its behavior at different input signals.
Following I post my testbench code, the only thing that I changed from the auto-generated code is the addition of the A and B signals (which I made like clock signals with different frequency).
-- Generated on "05/02/2021 16:58:30"
-- Vhdl Test Bench template for design : progetto_dsp_top
--
-- Simulation tool : ModelSim-Altera (VHDL)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY progetto_dsp_top_vhd_tst IS
END progetto_dsp_top_vhd_tst;
ARCHITECTURE progetto_dsp_top_arch OF progetto_dsp_top_vhd_tst IS
-- constants
constant period_A : time := 10 ps;
constant period_B : time := 20 ps;
-- signals
SIGNAL A : STD_LOGIC := '0';
SIGNAL B : STD_LOGIC := '0';
SIGNAL High : STD_LOGIC : '1';
SIGNAL QA : STD_LOGIC;
SIGNAL QB : STD_LOGIC;
COMPONENT progetto_dsp_top
PORT (
A : IN STD_LOGIC;
B : IN STD_LOGIC;
High : IN STD_LOGIC;
QA : OUT STD_LOGIC;
QB : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
--signal A generation
process
begin
A <= '1';
wait for period_A/2;
A <= '0';
wait for period_A/2;
if end_sim_s = true then
wait; -- end of simulation
end if;
end process;
signal B generation
process
begin
B <= '1';
wait for period_B/2;
B <= '0';
wait for period_B/2;
if end_sim_s = true then
wait; -- end of simulation
end if;
end process;
i1 : progetto_dsp_top
PORT MAP (
-- list connections between master ports and signals
A => A,
B => B,
High => High,
QA => QA,
QB => QB
);
init : PROCESS
-- variable declarations
BEGIN
-- code that executes only once
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
WAIT;
END PROCESS always;
END progetto_dsp_top_arch;