Multiply Accumulate Unit - vhdl

Question

I have a MAC unit for a transport triggered architecture processor, but for some reason. the multiply-accumulate part isn't working. I tested it separately and it worked, but when simulated out_reg_int is always 0 even though op_a and op_b are the correct values and I have included Numeric_STD.
-- These are just for the question
num_in_reg := 2;
num_reg := 4;
data_size := 71;
data_width := 64;
SIGNAL op_a, op_b : SIGNED(data_width-1 DOWNTO 0);
Signal out_reg_int, out_reg_out_int : SIGNED((data_width*2)-1 DOWNTO 0);
TYPE bus_array3 IS ARRAY (num_reg-1 DOWNTO num_in_reg) OF Signed(data_width-1 DOWNTO 0);
SIGNAL out_reg_in: bus_array3; -- for output register inputs
SIGNAL result: bus_array3; -- for results
op_a <= SIGNED(reg_out(0)(data_width-1 DOWNTO 0)); -- operand A
op_b <= SIGNED(reg_out(1)(data_width-1 DOWNTO 0)); -- operand B (trigger register)
-- Multiply Accumulate Operation
out_reg_int <= (op_a * op_b) + out_reg_out_int; -- multiply operands and add to current result
out_reg_out_int <= result(3) & result(2); -- combining the output registers lower and higher parts
out_reg_in(2) <= out_reg_int(data_width-1 downto 0); -- lower part of the result
out_reg_in(3) <= out_reg_int((data_width*2)-1 downto data_width); -- upper part of the result
------------------------------------------------------
-- Basically a register for pre place and route simulation.
------------------------------------------------------
result_regs: FOR J IN num_in_reg TO num_reg-1 GENERATE
Razor_result : entity work.Razor(Behavioral)
Generic Map (data_size => data_width)
Port Map (clk => CLK,
rst => Test_rst,
data => std_logic_vector(out_reg_in(J)),
wen => out_reg_en(J),
signed(data_out) => result(J),
error => Razor_error_int(J));
End Generate;
In the Testbench op_a is x64 and op_b is x100 and out_reg_int, out_reg_in and out_reg_out_int are all 0.
The full code for the unit is This :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.DigEng.All;
entity MAC is
Generic (data_size : INTEGER := 71; -- size of data
num_in_reg: INTEGER := 2; -- number of input registers
data_width: INTEGER := 64; --size of data minus parity bits
num_reg : INTEGER := 4);-- number of input and output registers
PORT (CLK : IN STD_LOGIC;
rst : IN STD_LOGIC; -- reset
en_all : IN STD_LOGIC; -- enable for all sequential elements
test_mode : IN STD_LOGIC; -- Hamming Fault Tolerance Testing
reg_input : IN STD_LOGIC_VECTOR(data_size-1 downto 0);
reg_output : OUT STD_LOGIC_VECTOR(data_size-1 downto 0);
error_en : IN STD_LOGIC; -- Hamming Error enable
we_regs : IN STD_LOGIC_VECTOR(num_reg-1 DOWNTO 0); -- registers write enable
re_regs : IN STD_LOGIC_VECTOR(num_reg-1 DOWNTO 0); -- registers read enable
Razor_error : OUT STD_LOGIC; -- Timing error occured
HW_Error : OUT STD_LOGIC); -- Error signal for FU replacement
end MAC;
architecture Behavioral of MAC is
---------------------------
-- Components declaration
---------------------------
-- Declaring D flipflop
COMPONENT d_ff IS
PORT(clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
en : IN STD_LOGIC;
data: IN STD_LOGIC;
q : OUT STD_LOGIC);
END COMPONENT;
--------------------
-- Internal signals
--------------------
-- Type declaration to array of buses for Outputs of all registers
TYPE bus_array IS ARRAY (num_reg-1 DOWNTO 0) OF STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
SIGNAL reg_out: bus_array; -- for registers outputs
TYPE bus_array4 IS ARRAY (num_in_reg-1 DOWNTO 0) OF STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
SIGNAL reg_input_int: bus_array4; -- for registers outputs
TYPE bus_array3 IS ARRAY (num_reg-1 DOWNTO num_in_reg) OF Signed(data_width-1 DOWNTO 0);
SIGNAL out_reg_in: bus_array3; -- for output register inputs
SIGNAL result: bus_array3; -- for results
TYPE bus_array5 IS ARRAY (num_reg-1 DOWNTO num_in_reg) OF STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
Signal post_op_hamming_in : bus_array5;
-- Input registers enables
TYPE reg_en IS ARRAY (num_in_reg-1 DOWNTO 0) OF STD_LOGIC;
SIGNAL in_reg_en: reg_en;
-- Output registers enables
TYPE reg_en2 IS ARRAY (num_reg-1 DOWNTO num_in_reg) OF STD_LOGIC;
SIGNAL out_reg_en: reg_en2;
-- Oprand A, operand B and operation trigger
SIGNAL op_a, op_b : SIGNED(data_width-1 DOWNTO 0);
Signal test_Input1, test_Input2, test_Output_High, test_Output_low : STD_LOGIC_VECTOR(data_width-1 DOWNTO 0);
SIGNAL t_op, test_rst, test_en, test_rst_int, test_en_delayed : STD_LOGIC; -- enable for the output registers
Signal out_reg_int, out_reg_out_int : SIGNED((data_width*2)-1 DOWNTO 0);
SIGNAL In_Hamming_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
Signal Razor_error_int : STD_LOGIC_VECTOR(Num_reg-1 downto 0);
BEGIN
-----------------------------------------------
-- Logic for the sequential elements enable
-----------------------------------------------
-- For input registers
input_regs_en: FOR H IN 0 TO num_in_reg-1 GENERATE
in_reg_en(H) <= (we_regs(H) AND en_all) OR Test_en;
END GENERATE;
-- Instantiate D flipflop
Inst_d_ff: d_ff
PORT MAP(clk => clk ,
rst => rst,
en => en_all, -- delay the trigger signal for a clock cycle
data => we_regs(1), -- delayed reg(1) write enable is used as trigger
q => t_op);
-- For output registers
output_regs_en: FOR I IN num_in_reg TO num_reg-1 GENERATE
out_reg_en(I) <= (t_op AND we_regs(1) AND en_all) OR Test_en ;
END GENERATE;
-------------------------------------------------
-- Instantiate hamming module to check input data
-------------------------------------------------
In_Hamming_module: entity work.Hamming_Module(Behavioral)
Generic Map (data_size => data_size)
PORT MAP(Data_in => reg_input,
Data_out => In_Hamming_out,
Error_en => error_en,
Error_sig => OPEN);
--------------------------------------------------------
-- Razor Shadow Latch Unit for checking Timing on Input
--------------------------------------------------------
input_regs: FOR J IN 0 TO num_in_reg-1 GENERATE
Razor_In : entity work.Razor(Behavioral)
Generic Map (data_size => data_size)
Port Map (clk => CLK,
rst => rst,
data => reg_input_int(J),
wen => in_reg_en(J),
data_out => reg_out(J),
error => Razor_error_int(J));
END GENERATE;
------------------------------------------------------
-- Razor Shadow Latch Unit for checking Timing post OP
------------------------------------------------------
result_regs: FOR J IN num_in_reg TO num_reg-1 GENERATE
Razor_result : entity work.Razor(Behavioral)
Generic Map (data_size => data_width)
Port Map (clk => CLK,
rst => Test_rst,
data => std_logic_vector(out_reg_in(J)),
wen => out_reg_en(J),
signed(data_out) => result(J),
error => Razor_error_int(J));
End Generate;
------------------------------------------------------
-- Instantiate hamming module to recalculate
-- parity values after operations
------------------------------------------------------
hamming_post_ops: FOR J IN num_in_reg TO num_reg-1 GENERATE
post_op_hamming_in(J) <= std_logic_vector(resize(result(J), data_size));
hamming_post_ops: entity work.Hamming_Module(Behavioral)
Generic Map (data_size => data_size)
PORT MAP(Data_in => post_op_hamming_in(J),
Data_out => reg_out(J),
Error_en => '0',
Error_sig => OPEN);
End Generate;
----------------------------
-- MAC Testing
----------------------------
Mac_Tester_Unit : entity work.MAC_Tester(Behavioral)
Generic Map(data_size => data_size, -- size of data
num_in_reg => num_in_reg, -- number of input registers
data_width => data_width, -- size of data minus parity bits
num_reg => num_reg) -- number of input and output registers)
Port Map(clk => clk,
en_all => Test_en,
Input_reg1 => test_Input1,
Input_reg2 => test_Input2,
Output_reg_lower => test_Output_High,
Output_reg_higher => test_Output_low,
rst => test_rst_int);
--------------------------------------------------------
-- Assigning the output of input registers to operands
--------------------------------------------------------
op_a <= SIGNED(reg_out(0)(data_width-1 DOWNTO 0)); -- operand A
op_b <= SIGNED(reg_out(1)(data_width-1 DOWNTO 0)); -- operand B (trigger register)
-- Multiply Accumulate Operation
out_reg_int <= (op_a * op_b) + out_reg_out_int; -- multiply operands and add to current result
out_reg_out_int <= result(3) & result(2); -- combining the output registers lower and higher parts
out_reg_in(2) <= out_reg_int(data_width-1 downto 0); -- lower part of the result
out_reg_in(3) <= out_reg_int((data_width*2)-1 downto data_width); -- upper part of the result
----------------------------------------------------------------
-- Tri-state buffer to output the chosen register output to the
-- central data bus
----------------------------------------------------------------
connections2: FOR J IN num_in_reg TO num_reg-1 GENERATE
reg_output <= reg_out(J) WHEN re_regs(J) = '1' ELSE (OTHERS => 'Z');
END GENERATE;
Razor_error <= Razor_error_int(0) OR Razor_error_int(1) OR Razor_error_int(2) OR Razor_error_int(3);
-----------------------------
-- Test Vector Assignment
-----------------------------
Test_en <= '1' When we_regs = "0000" AND re_regs = "0000" AND en_all = '1' AND error_en = '1' else '0';
Test_rst <= Test_rst_int When Test_en = '1' else rst;
reg_input_int(0)(data_width-1 downto 0) <= test_Input1 when Test_en = '1' else
In_Hamming_out(data_width-1 downto 0);
reg_input_int(1)(data_width-1 downto 0) <= test_Input2 when Test_en = '1' else
In_Hamming_out(data_width-1 downto 0);
------------------------------------------------------
-- Instantiate D flipflop for delaying output testing
------------------------------------------------------
Test_d_ff: d_ff
PORT MAP(clk => clk ,
rst => rst,
en => en_all,
data => Test_en, -- delay Test_en for 1 clock cycle for output check
q => Test_en_delayed);
HW_Error <= '0' When Test_en_delayed <= '0' OR (signed(test_Output_High) = result(3) AND signed(test_Output_low) = result(2)) else
'1';
end Behavioral;