Finite State Machine with Its States Controlled by Two Processes - vhdl

Question

I'm trying to code a finite state machine (FSM) with VHDL language right now (and I'm actually new to VHDL). What I'm trying to achieve is, whenever the machine is in S11, the STint will decrease respectively with the CLK2 (So I can control how fast the decreasement is). However, S0 until S10 are controlled by CLK1.
Here is my code:
begin
process(state,DI,HI,QI,rst)
begin
case State is
when S0 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '0'; STint <= 9;
if DI'EVENT and DI = '1' then Nextstate <= S4;
elsif HI'EVENT and HI = '1' then Nextstate <= S2;
elsif QI'EVENT and QI = '1' then Nextstate <= S1;
elsif rst'EVENT and rst = '1' then Nextstate <= S10;
else Nextstate <= S0; end if;
when S1 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '0';
if DI'EVENT and DI = '1' then Nextstate <= S5;
elsif HI'EVENT and HI = '1' then Nextstate <= S3;
elsif QI'EVENT and QI = '1' then Nextstate <= S2;
elsif rst'EVENT and rst = '1' then Nextstate <= S10;
else Nextstate <= S1; end if;
when S2 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '0';
if DI'EVENT and DI = '1' then Nextstate <= S6;
elsif HI'EVENT and HI = '1' then Nextstate <= S4;
elsif QI'EVENT and QI = '1' then Nextstate <= S3;
elsif rst'EVENT and rst = '1' then Nextstate <= S10;
else Nextstate <= S2; end if;
when S3 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '0';
if DI'EVENT and DI = '1' then Nextstate <= S7;
elsif HI'EVENT and HI = '1' then Nextstate <= S5;
elsif QI'EVENT and QI = '1' then Nextstate <= S4;
elsif rst'EVENT and rst = '1' then Nextstate <= S10;
else Nextstate <= S3; end if;
when S4 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '0';
if DI'EVENT and DI = '1' then Nextstate <= S8;
elsif HI'EVENT and HI = '1' then Nextstate <= S6;
elsif QI'EVENT and QI = '1' then Nextstate <= S5;
elsif rst'EVENT and rst = '1' then Nextstate <= S10;
else Nextstate <= S4; end if;
when S5 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '0';
if DI'EVENT and DI = '1' then Nextstate <= S9;
elsif HI'EVENT and HI = '1' then Nextstate <= S7;
elsif QI'EVENT and QI = '1' then Nextstate <= S6;
elsif rst'EVENT and rst = '1' then Nextstate <= S10;
else Nextstate <= S5; end if;
when S6 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '0';
Nextstate <= S11;
when S7 =>
DO <= '0'; HO <= '0'; QO <= '1'; ST <= '0';
QOint <= -1;
Nextstate <= S11;
when S8 =>
DO <= '0'; HO <= '1'; QO <= '0'; ST <= '0';
HOint <= HOint -1;
Nextstate <= S11;
when S9 =>
DO <= '0'; HO <= '1'; QO <= '1'; ST <= '0';
HOint <= HOint -1;
QOint <= QOint -1;
Nextstate <= S11;
when S10 =>
DOint <= 9; HOint <= 9; QOint <= 9; STint <= 9;
Nextstate <= S0;
when others => null;
end case;
end process;
process(CLK1)
begin
if CLK1'EVENT and CLK1 = '1' then
State <= Nextstate;
end if;
end process;
process(state,CLK2)
begin
case State is
when S11 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '1';
if CLK2'EVENT and CLK2 = '1' then STint <= STint -1;
elsif STint <= 0 then Nextstate <= S0; end if;
when others => null;
end case;
end process;
I've tried many alternatives, such as using the CLK1 as the clock for the STint decreasement, but it didn't work well because the other int(s) will decrease again and again.
For further information, this FSM is actually similar to vending machine, except in S11, a timer will start the countdown then go to the next state, which is S0. The other states is just for the inputs (such as the money) and the outputs (such as the changes). In S11, the ST LED will be turned on as long as the timer still counting down.
Is there any way I can achieve this? I would really glad if someone could point me out why my code won't work. It seems like whenever the machine is in S11, it cannot change its state. This is how my code looks like in TINA:
Thank you very much. Have a nice day!
PS: The timer is shown in STcount outputs

Answer 1

You have some issues in your approach:
Multiple clocks for the FSM. You should avoid to have multiple clocks in your designs and use it only when necessary. To have two clocks for a given circuit is ask for problems.
Use a single clock. If you want to keep the control using the clock build a separate circuit to control just the clock generation. A counter can solve for a simple design. More complex design may require the use of specific hardware for clock generation(e.g PLL).
You are assigning to signals in different process at least DO. This should not synthesize.
I suggest you to rethink your state machine control and to understand the limits for the decreasing speed.