I'm working on project which should convert data from analog to digital with approximation and I have error when i try compile code in Quartus II 9.1sp2 Web Edition which is shown in title with Case Statement in the code below:
architecture behavior of adc is
type state is (reset, state1, state2, state3, state4, state5, state6, state7, state8, state9, state10);
signal nx_state : state;
begin
process (in_clk, rst_n, start)
begin
if(rst_n'event and rst_n='0') then
B_hold <= "1111";
D_out <= "0000";
data_out <= "0000";
hold <= '1';
sample <= '0';
eoc <= '0';
if start = '1' then
nx_state <= state1;
else
nx_state <= reset;
end if;
elsif(in_clk'event and in_clk='1') then
case nx_state is
when state1 => nx_state <= state2;
B_hold <= "0000";
hold <= '0';
sample <= '1';
when state2 => nx_state <= state3;
B_hold <= "1111";
D_out <= "0000";
when state3 => nx_state <= state4;
B_hold(3) <= '0';
D_out(3) <= '1';
data_out(3) <= '1';
when state4 => nx_state <= state5;
if comp_in = '1' then
B_hold(3) <= '0';
D_out(3) <= '1';
data_out(3) <= '1';
else
B_hold(3) <= '1';
D_out(3) <= '0';
data_out(3) <= '0';
end if;
when state5 => nx_state <= state6;
B_hold(2) <= '0';
D_out(2) <= '1';
data_out(2) <= '1';
when state6 => nx_state <= state7;
if comp_in = '1' then
B_hold(2) <= '0';
D_out(2) <= '1';
data_out(2) <= '1';
else
B_hold(2) <= '1';
D_out(2) <= '0';
data_out(2) <= '0';
end if;
when state7 => nx_state <= state8;
B_hold(1) <= '0';
D_out(1) <= '1';
data_out(1) <= '1';
when state8 => nx_state <= state9;
if comp_in = '1' then
B_hold(1) <= '0';
D_out(1) <= '1';
data_out(1) <= '1';
else
B_hold(1) <= '1';
D_out(1) <= '0';
data_out(1) <= '0';
end if;
when state9 => nx_state <= state10;
B_hold(0) <= '0';
D_out(0) <= '1';
data_out(0) <= '1';
when state10 => nx_state <= reset;
if comp_in = '1' then
B_hold(0) <= '0';
D_out(0) <= '1';
data_out(0) <= '1';
else
B_hold(0) <= '1';
D_out(0) <= '0';
data_out(0) <= '0';
end if;
eoc <= '1';
end case;
end if;
end process;
end behavior;
I'm new newbie at vhdl and I don't know what exactly is wrong with the conditions shown above.
Your type includes a state named reset. You need a when for that state.
case nx_state is
when reset =>
Reset is level sensitive. So change
if(rst_n'event and rst_n='0') then
to
if(rst_n='0') then
It is also unusual to have a condition within the reset condition
if start = '1' then
nx_state <= state1;
else
nx_state <= reset;
end if;
Hence, you probably just want:
nx_state <= reset;
Related
I'm trying to implement a testbench for the following fsm in created in vhdl. The problem is that currently, I'm not seeing any state transitions in the test bench. The simulation stays at state 0.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FPGA_Challenge is
Port ( led : out STD_LOGIC;
clk_in : in STD_LOGIC; -- 100 MHZ internal clock
reset : in STD_LOGIC; -- is reset necessary
button : in STD_LOGIC;
data_line : in STD_LOGIC);
end FPGA_Challenge;
architecture Behavioral of FPGA_Challenge is
type state_type is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20);
signal state: state_type;
signal x:std_logic;
signal y:std_logic;
signal count : integer:= 0;
--signal tmp: std_logic:= '1';
begin
process(clk_in, reset)
begin
if rising_edge(clk_in)then
if reset = '1'then -- Goes back to known state (state 0)
state <= s0;
count <= 0;
else
count <= count + 1;
case state is
-- Initial state- if button is pressed, then LED is lit and machine goes to state 2, if not it stays in state 1
when s0 =>
if (button <= '1') then
led <= '1';
state <= s1;
else
state <= s0;
led <= '0'; --is this necessary?
end if;
-- Beginning of preamble detection(states 1-17)
-- Count = ((freq in) / (freq out))/ 2 -1 = (100 MHz/ 2 MHz)/ 2 -1 = 50/2 - 1 (due to 50% duty cycle)
when s1=> -- do I need to put led = '1' in each state because it stays on ?
if (count = 25 -1) then
count <= 0;
if (data_line = '1')then
y <= '0';
-- led = '1';
state <= s2;
else
-- led = '1';
y <= '0';
state <= s1;
end if;
else
count <= count + 1;
end if;
--clock_out <= tmp;
when s2 =>
if (count = 25-1) then
count <= 0;
if (data_line = '0')then
y <= '0';
-- led = '1';
state <= s3;
else
state <= s2;
y <= '0';
-- led = '1';
end if;
else
count <= count + 1;
end if;
--clock_out <= tmp;
when s3 =>
if (count = 25-1)then
count <= 0; ----reinitializes count
if (data_line <= '1')then
y <= '0';
-- led = '1';
state <= s4;
else
state <= s1;
y <= '0';
-- led = '1';
end if;
else
count <= count + 1;
end if;
-- clock_out <= tmp;
when s4 =>
if (count = 25-1)then
count <= 0;
if (data_line <='0')then
y <= '0';
--led = '1';
state <= s5;
else
state <= s2;
y <= '0';
--led = '1';
end if;
else
count <= count + 1;
end if;
-- clock_out <= tmp;
when s5 =>
if (count = 25-1)then
count <= 0;
if (data_line <='0')then
y <= '0';
--led = '1';
state <= s6;
else
state <= s4;
y <= '0';
--led = '1';
end if;
else
count <= count + 1;
end if;
--clock_out <= tmp;
when s6 =>
if (count= 25-1)then
count <= 0;
if (data_line <='0')then
y <= '0';
--led = '1';
state <= s7;
else
state <= s2;
y <= '0';
--led = '1';
end if;
else
count <= count + 1;
end if;
-- clock_out <= tmp;
when s7 =>
if (count = 25-1)then
count<= 0;
if (data_line <='0')then
y <= '0';
--led = '1';
state <= s7;
else
state <= s2;
y <= '0';
--led = '1';
end if;
else
count <= count + 1;
end if;
--clock_out <= tmp;
when s8 =>
if (count = 25-1)then
count <= 0;
if (data_line <='1')then
y <= '0';
-- led = '1';
state <= s9;
else
state <= s1;
y <= '0';
--led = '1';
end if;
else
count <= count + 1;
end if;
-- clock_out <= tmp;
when s9 =>
if (count = 25-1)then
count <= 0;
if (data_line <='0')then
y <= '0';
-- led = '1';
state <= s10;
else
state <= s2;
y <= '0';
--led = '1';
end if;
else
count <= count + 1;
end if;
--clock_out <= tmp;
when s10=>
if (count = 25-1)then
count <= 0;
if (data_line <='1')then
y <= '0';
--led = '1';
state <= s11;
else
state <= s1;
y <= '0';
--led = '1';
end if;
else
count <= count + 1;
end if;
-- clock_out <= tmp;
when s11 =>
if (count = 25-1)then
count <= 0;
if (data_line <='0')then
y <= '0';
--led = '1';
state <= s12;
else
state <= s2;
y <= '0';
--led = '1';
end if;
else
count <= count + 1;
end if;
--clock_out <= tmp;
when s12 =>
if (count = 25-1)then
count <= 0;
if (data_line <='0')then
y <= '0';
--led = '1';
state <= s13;
else
state <= s2;
y <= '0';
--led = '1';
end if;
else
count <= count + 1;
end if;
-- clock_out <= tmp;
when s13 =>
if (count = 25-1)then
count <= 0;
if (data_line <='0')then
y <= '0';
-- led = '1';
state <= s14;
else
state <= s2;
y <= '0';
-- led = '1';
end if;
else
count <= count + 1;
end if;
-- clock_out <= tmp;
when s14 =>
if (count = 25-1)then
count <=0;
if (data_line <='0')then
y <= '0';
-- led = '1';
state <= s15;
else
state <= s2;
y <= '0';
-- led = '1';
end if;
else
count <= count + 1;
end if;
--clock_out <= tmp;
when s15 =>
if (count = 25-1)then
count <=0;
if (data_line <='0') then
y <= '0';
-- led = '1';
state <= s16;
else
state <= s2;
y <= '0';
-- led = '1';
end if;
else
count <= count + 1;
end if;
-- clock_out <= tmp;
when s16 =>
if (count = 25-1) then
count <= 0;
if (data_line <='0')then
y <= '0';
-- led = '1';
state <= s17;
else
state <= s2;
y <= '0';
-- led = '1';
end if;
else
count <= count + 1;
end if;
--clock_out <= tmp;
when s17 =>
if (count = 25-1)then
count <= 0;
if (data_line ='1')then
y <= '1';
-- led = '1';
state <= s18;
else
state <= s1;
y <= '0';
--led = '1';
end if;
else
count <= count + 1;
end if;
--clock_out <= tmp;
when s18 => -- no real condition here except varying period of clock
if (count = 25)then
count <= 0; ----reinitializes count
state <= s19;
else
count <= count + 1;
end if;
-- clock_out <= tmp;
when s19=> -- no real condition here except varying period of clock
if (count = 25)then
count <= 0; ----reinitializes count
state <= s0;
else
count <= count + 1;
end if;
--clock_out <= tmp;
when others=>
null;
end case;
end if;
end if;
end process;
end architecture;
The following is the testbench I have so far. I have internal signals such as y(output for each state), and count(counter for how long I'm in a state) that I probably should be using as drivers in the testbench. Any input is appreciated
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FPGA_tb is
-- Port ( );
end FPGA_tb;
architecture Behavioral of FPGA_tb is
component FPGA_Challenge is
Port( led : out STD_LOGIC;
clk_in : in STD_LOGIC; -- 100 MHZ internal clock
reset : in STD_LOGIC; -- is reset necessary
button : in STD_LOGIC;
data_line : in STD_LOGIC);
end component;
signal led : STD_LOGIC;
signal clk_in : STD_LOGIC; -- 100 MHZ internal clock
signal reset : STD_LOGIC; -- is reset necessary
signal button : STD_LOGIC;
signal data_line : STD_LOGIC;
type state_type is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20);
signal state: state_type;
signal x,y: std_logic;
signal count : integer:= 0;
begin
UUT: FPGA_Challenge
PORT MAP(
led => led,
clk_in => clk_in,
reset => reset,
button => button,
data_line => data_line
);
Testing: Process
begin
--wait until rising_edge(clk_in);
--wait until rising_edge(clk_in);
clk_in <='0';
reset <= '1';
button <= '0';
data_line <= '0';
WAIT For 10ns;
clk_in <='1';
reset <= '0';
button <= '1';
data_line <= '0';
WAIT For 10ns;
clk_in <='1';
reset <= '1';
button <= '0';
data_line <= '1';
WAIT For 10ns;
clk_in <='0';
reset <= '1';
button <= '0';
data_line <= '0';
WAIT For 10ns;
clk_in <='1';
reset <= '1';
button <= '0';
data_line <= '0';
WAIT For 10ns;
end process;
end Behavioral;
Try this in the testbench to have a running clock and proper reset
signal clk_in : STD_LOGIC := '1'; -- 100 MHZ internal clock
signal reset : STD_LOGIC := '1'; -- is reset necessary
clk_in <=NOT clk_in after 10ns;
reset <= 0 after 30ns;
play with button after the reset. that is, from 40ns
My code generates two latches, could please someone help me finding why?
According to Xilinx ISE latches are generated because of "try_counter" which is a counter for how many times you get a numeric sequence wrong. (which is the main point of my code).
I don't know what else to do.
entity moore is
Port ( badgeSx : in STD_LOGIC;
badgeDx : in STD_LOGIC;
col : in std_logic_vector (1 to 3);
row : in std_logic_vector (1 to 4);
clk : in std_logic;
rst : in std_logic;
unlock : out STD_LOGIC
);
end moore;
architecture Behavioral of moore is
type stato is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9);
signal current_state,next_state : stato;
signal badge : std_logic_vector(1 downto 0);
signal count, new_count: integer range 0 to 28;
signal temp_unlock : std_logic :='0';
signal timeover : std_logic :='0';
begin
badge <= badgeDx & badgeSx; --concatenazione dei badge
--processo sequenziale
current_state_register: process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
current_state <= s0;
count <= 0;
else
current_state <= next_state;
count <= new_count;
end if;
end if;
end process;
process (current_state,badge,col,row,timeover)
variable try_counter: integer range 0 to 3;
begin
case current_state is
when s0 =>
try_counter := 0;
temp_unlock <= '0';
unlock <='0';
if(badge ="01" and row = "0000" and col = "000" ) then
next_state <= s1;
else
next_state <= s0;
end if;
when s1 =>
temp_unlock <= '1';
unlock <= '0';
if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
next_state <= s2;
elsif (timeover ='1' or badge = "10" or try_counter = 3) then
next_state <= s0;
else
next_state <= s1;
try_counter := try_counter +1;
end if;
when s2 =>
temp_unlock <= '0';
unlock <='0';
if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
next_state <= s2;
else
next_state <= s3;
end if;
when s3 =>
temp_unlock <= '1';
unlock <= '0';
if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
next_state <= s4;
elsif (timeover ='1' or badge = "10" or try_counter = 3) then
next_state <= s0;
else
next_state <= s1;
try_counter := try_counter +1;
end if;
when s4 =>
temp_unlock <= '0';
unlock <='0';
if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
next_state <= s4;
else
next_state <= s5;
end if;
when s5 =>
temp_unlock <= '1';
unlock <= '0';
if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
next_state <= s6;
elsif (timeover ='1' or badge = "10" or try_counter = 3) then
next_state <= s0;
else
next_state <= s1;
try_counter := try_counter +1;
end if;
when s6 =>
temp_unlock <= '0';
unlock <='0';
if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
next_state <= s6;
else
next_state <= s7;
end if;
when s7 =>
temp_unlock <= '1';
unlock <= '0';
if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
next_state <= s8;
elsif (timeover ='1' or badge = "10" or try_counter = 3) then
next_state <= s0;
else
next_state <= s1;
try_counter := try_counter +1;
end if;
when s8 =>
temp_unlock <= '0';
unlock <='0';
if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
next_state <= s8;
else
next_state <= s9;
end if;
when s9 =>
temp_unlock <= '0';
unlock <= '1';
if (badge = "10") then
next_state <= s0;
else
next_state <= s5;
end if;
when others =>
next_state <= s0;
end case;
end process;
Contatore_TIMER : process(temp_unlock,count)
begin
if temp_unlock = '1' then
if count = 28 then
new_count<=0;
timeover<='1';
else
new_count<=count+1;
timeover<='0';
end if;
else
new_count<=0;
timeover <= '0';
end if;
end process;
end Behavioral;
The code nearly works as expected (I mean it compiles and I don't get any error) but the RTL schematic isn't what it is supposed to be since it synthesises latches in the process.
In the apparently combinatorial process with process (current_state,badge,col,row,timeover), the variable try_counter is used to store information (sequential behaviour), which is only updated when process evaluation is triggered. This will very likely to generate the 2 latches, which matches the value range from 0 to 3 for try_counter.
To fix this, you can define try_counter as a signal, and include it in the sensitivity list for the process.
Having try_counter as a signal will also ease debugging, since the current state can easily be inspected in waveforms.
I'm trying to code a finite state machine (FSM) with VHDL language right now (and I'm actually new to VHDL). What I'm trying to achieve is, whenever the machine is in S11, the STint will decrease respectively with the CLK2 (So I can control how fast the decreasement is). However, S0 until S10 are controlled by CLK1.
Here is my code:
begin
process(state,DI,HI,QI,rst)
begin
case State is
when S0 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '0'; STint <= 9;
if DI'EVENT and DI = '1' then Nextstate <= S4;
elsif HI'EVENT and HI = '1' then Nextstate <= S2;
elsif QI'EVENT and QI = '1' then Nextstate <= S1;
elsif rst'EVENT and rst = '1' then Nextstate <= S10;
else Nextstate <= S0; end if;
when S1 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '0';
if DI'EVENT and DI = '1' then Nextstate <= S5;
elsif HI'EVENT and HI = '1' then Nextstate <= S3;
elsif QI'EVENT and QI = '1' then Nextstate <= S2;
elsif rst'EVENT and rst = '1' then Nextstate <= S10;
else Nextstate <= S1; end if;
when S2 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '0';
if DI'EVENT and DI = '1' then Nextstate <= S6;
elsif HI'EVENT and HI = '1' then Nextstate <= S4;
elsif QI'EVENT and QI = '1' then Nextstate <= S3;
elsif rst'EVENT and rst = '1' then Nextstate <= S10;
else Nextstate <= S2; end if;
when S3 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '0';
if DI'EVENT and DI = '1' then Nextstate <= S7;
elsif HI'EVENT and HI = '1' then Nextstate <= S5;
elsif QI'EVENT and QI = '1' then Nextstate <= S4;
elsif rst'EVENT and rst = '1' then Nextstate <= S10;
else Nextstate <= S3; end if;
when S4 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '0';
if DI'EVENT and DI = '1' then Nextstate <= S8;
elsif HI'EVENT and HI = '1' then Nextstate <= S6;
elsif QI'EVENT and QI = '1' then Nextstate <= S5;
elsif rst'EVENT and rst = '1' then Nextstate <= S10;
else Nextstate <= S4; end if;
when S5 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '0';
if DI'EVENT and DI = '1' then Nextstate <= S9;
elsif HI'EVENT and HI = '1' then Nextstate <= S7;
elsif QI'EVENT and QI = '1' then Nextstate <= S6;
elsif rst'EVENT and rst = '1' then Nextstate <= S10;
else Nextstate <= S5; end if;
when S6 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '0';
Nextstate <= S11;
when S7 =>
DO <= '0'; HO <= '0'; QO <= '1'; ST <= '0';
QOint <= -1;
Nextstate <= S11;
when S8 =>
DO <= '0'; HO <= '1'; QO <= '0'; ST <= '0';
HOint <= HOint -1;
Nextstate <= S11;
when S9 =>
DO <= '0'; HO <= '1'; QO <= '1'; ST <= '0';
HOint <= HOint -1;
QOint <= QOint -1;
Nextstate <= S11;
when S10 =>
DOint <= 9; HOint <= 9; QOint <= 9; STint <= 9;
Nextstate <= S0;
when others => null;
end case;
end process;
process(CLK1)
begin
if CLK1'EVENT and CLK1 = '1' then
State <= Nextstate;
end if;
end process;
process(state,CLK2)
begin
case State is
when S11 =>
DO <= '0'; HO <= '0'; QO <= '0'; ST <= '1';
if CLK2'EVENT and CLK2 = '1' then STint <= STint -1;
elsif STint <= 0 then Nextstate <= S0; end if;
when others => null;
end case;
end process;
I've tried many alternatives, such as using the CLK1 as the clock for the STint decreasement, but it didn't work well because the other int(s) will decrease again and again.
For further information, this FSM is actually similar to vending machine, except in S11, a timer will start the countdown then go to the next state, which is S0. The other states is just for the inputs (such as the money) and the outputs (such as the changes). In S11, the ST LED will be turned on as long as the timer still counting down.
Is there any way I can achieve this? I would really glad if someone could point me out why my code won't work. It seems like whenever the machine is in S11, it cannot change its state. This is how my code looks like in TINA:
Thank you very much. Have a nice day!
PS: The timer is shown in STcount outputs
You have some issues in your approach:
Multiple clocks for the FSM. You should avoid to have multiple clocks in your designs and use it only when necessary. To have two clocks for a given circuit is ask for problems.
Use a single clock. If you want to keep the control using the clock build a separate circuit to control just the clock generation. A counter can solve for a simple design. More complex design may require the use of specific hardware for clock generation(e.g PLL).
You are assigning to signals in different process at least DO. This should not synthesize.
I suggest you to rethink your state machine control and to understand the limits for the decreasing speed.
My code is intended to be purely combinational. Only one element gives some synchronysm to simulation. it is a 4*4 led matrix where only 3*3 (starting on the top right) is valid. like:
-- LED matrix
-- rows\cols | A | B | C | D |
---------------------------------
-- 1 | 3 | 2 | 1 | 0 |
-- 2 | 7 | 6 | 5 | 4 |
-- 3 | 11 | 10| 9 | 8 |
-- 4 | 15 | 14| 13| 12| <- row not used
-- ^
-- |
-- column not used
---------------------------------
the following code compiles and simulates on an FPGA but not with the desired behaviour. The wanted behabiour is to iluminate a red led if one input is detected, 2 if 2, and if 3 are in a row in the matrix at the same time instead of 3 red led it should show 3 blue ones. no memory involved. The observed behaviour is explained as coments within the code.
entity mt is
PORT (
cD, cC, cB, cA : in std_logic; -- comparators for each column. cA is not necessary / not used.
row : inout std_logic_vector (3 downto 0) := (others => '0'); -- detection of each row.
led_R, led_G, led_B : out std_logic_vector (15 downto 0) := (others => '1') -- '1' indicates they are OFF. 12 to 15 will not be used (as well as 3, 7, 11 positions)
);
end mt;
I have 4 concurrent processes which depend on the signals explained:
architecture arc1 of mt is
signal led_R_in : std_logic_vector (15 downto 0) := (others => '1');
signal led_G_in : std_logic_vector (15 downto 0) := (others => '1'); -- don't think they are necessary
signal led_B_in : std_logic_vector (15 downto 0) := (others => '1'); -- don't think they are necessary
signal counter : std_logic_vector (1 downto 0) := "00";
begin
PROCESS (row, cD, cC, cB, cA) -- execute if any of these change
BEGIN
CASE row IS
WHEN "1000" => -- row 1 --
-- (LEDs are active at logic level 0)
CASE cD IS
WHEN '1' => led_R_in(0) <= '0'; led_G_in(0) <= '1'; led_B_in(0) <= '1';
WHEN OTHERS => led_R_in(0) <= '1'; led_G_in(0) <= '1'; led_B_in(0) <= '1';
END CASE;
CASE cC IS
WHEN '1' => led_R_in(1) <= '0'; led_G_in(1) <= '1'; led_B_in(1) <= '1';
WHEN OTHERS => led_R_in(1) <= '1'; led_G_in(1) <= '1'; led_B_in(1) <= '1';
END CASE;
CASE cB IS
WHEN '1' => led_R_in(2) <= '0'; led_G_in(2) <= '1'; led_B_in(2) <= '1';
WHEN OTHERS => led_R_in(2) <= '1'; led_G_in(2) <= '1'; led_B_in(2) <= '1';
END CASE;
CASE cA IS -- not necessary
WHEN '1' => led_R_in(3) <= '0'; led_G_in(3) <= '1'; led_B_in(3) <= '1';
WHEN OTHERS => led_R_in(3) <= '1'; led_G_in(3) <= '1'; led_B_in(3) <= '1';
END CASE;
WHEN "0100" => -- row 2 --
-- (LEDs are active at logic level 0)
CASE cD IS
WHEN '1' => led_R_in(4) <= '0'; led_G_in(4) <= '1'; led_B_in(4) <= '1';
WHEN OTHERS => led_R_in(4) <= '1'; led_G_in(4) <= '1'; led_B_in(4) <= '1';
END CASE;
CASE cC IS
WHEN '1' => led_R_in(5) <= '0'; led_G_in(5) <= '1'; led_B_in(5) <= '1';
WHEN OTHERS => led_R_in(5) <= '1'; led_G_in(5) <= '1'; led_B_in(5) <= '1';
END CASE;
CASE cB IS
WHEN '1' => led_R_in(6) <= '0'; led_G_in(6) <= '1'; led_B_in(6) <= '1';
WHEN OTHERS => led_R_in(6) <= '1'; led_G_in(6) <= '1'; led_B_in(6) <= '1';
END CASE;
CASE cA IS -- not necessary
WHEN '1' => led_R_in(7) <= '0'; led_G_in(7) <= '1'; led_B_in(7) <= '1';
WHEN OTHERS => led_R_in(7) <= '1'; led_G_in(7) <= '1'; led_B_in(7) <= '1';
END CASE;
WHEN "0010" => -- row 3 --
-- (LEDs are active at logic level 0)
CASE cD IS
WHEN '1' => led_R_in(8) <= '0'; led_G_in(8) <= '1'; led_B_in(8) <= '1';
WHEN OTHERS => led_R_in(8) <= '1'; led_G_in(8) <= '1'; led_B_in(8) <= '1';
END CASE;
CASE cC IS
WHEN '1' => led_R_in(9) <= '0'; led_G_in(9) <= '1'; led_B_in(9) <= '1';
WHEN OTHERS => led_R_in(9) <= '1'; led_G_in(9) <= '1'; led_B_in(9) <= '1';
END CASE;
CASE cB IS
WHEN '1' => led_R_in(10) <= '0'; led_G_in(10) <= '1'; led_B_in(10) <= '1';
WHEN OTHERS => led_R_in(10) <= '1'; led_G_in(10) <= '1'; led_B_in(10) <= '1';
END CASE;
CASE cA IS -- not necessary
WHEN '1' => led_R_in(11) <= '0'; led_G_in(11) <= '1'; led_B_in(11) <= '1';
WHEN OTHERS => led_R_in(11) <= '1'; led_G_in(11) <= '1'; led_B_in(11) <= '1';
END CASE;
WHEN OTHERS => Null; -- not necessary, although for avoiding latches creation I will have to assign them.
END CASE;
END PROCESS;
PROCESS (led_R_in) -- executes when led_R_in changes
BEGIN
-- leds are ON at '0' value
-- the problem is that, when initialising, the first row of leds will be blue, which means that
-- led_R_in 0, 1, 2 are 0, but they should be 1 as stated in their default values
-- the second and third row initialises correctly to green values, although the response to changes in the inputs are not only affecting them but also their neighbours, which I think it could be a problem of the FPGA pin assignment.
if (led_R_in(0)='0' AND ((led_R_in(1)='0' AND led_R_in(2)='0') OR (led_R_in(4)='0' AND led_R_in(8)='0') OR (led_R_in(5)='0' AND led_R_in(10)='0'))) then
led_B(0) <= '0';
led_R(0) <= '1';
led_G(0) <= '1';
else
led_R(0) <= led_R_in(0);
led_G(0) <= '0';
led_B(0) <= '1';
end if;
if (led_R_in(1)='0' AND ((led_R_in(0)='0' AND led_R_in(2)='0') OR (led_R_in(5)='0' AND led_R_in(9)='0'))) then
led_B(1) <= '0';
led_R(1) <= '1';
led_G(1) <= '1';
else
led_R(1) <= led_R_in(1);
led_G(1) <= '0';
led_B(1) <= '1';
end if;
if (led_R_in(2)='0' AND ((led_R_in(0)='0' AND led_R_in(1)='0') OR (led_R_in(10)='0' AND led_R_in(6)='0') OR (led_R_in(5)='0' AND led_R_in(8)='0'))) then
led_B(2) <= '0';
led_R(2) <= '1';
led_G(2) <= '1';
else
led_R(2) <= led_R_in(2);
led_G(2) <= '0';
led_B(2) <= '1';
end if;
if (led_R_in(4)='0' AND ((led_R_in(0)='0' AND led_R_in(8)='0') OR (led_R_in(5)='0' AND led_R_in(6)='0'))) then
led_B(4) <= '0';
led_R(4) <= '1';
led_G(4) <= '1';
else
led_R(4) <= led_R_in(4);
led_G(4) <= '0';
led_B(4) <= '1';
end if;
if (led_R_in(5)='0' AND ((led_R_in(2)='0' AND led_R_in(8)='0') OR (led_R_in(1)='0' AND led_R_in(9)='0') OR (led_R_in(0)='0' AND led_R_in(10)='0') OR (led_R_in(6)='0' AND led_R_in(4)='0'))) then
led_B(5) <= '0';
led_R(5) <= '1';
led_G(5) <= '1';
else
led_R(5) <= led_R_in(5);
led_G(5) <= '0';
led_B(5) <= '1';
end if;
if (led_R_in(6)='0' AND ((led_R_in(2)='0' AND led_R_in(10)='0') OR (led_R_in(5)='0' AND led_R_in(4)='0'))) then
led_B(6) <= '0';
led_R(6) <= '1';
led_G(6) <= '1';
else
led_R(6) <= led_R_in(6);
led_G(6) <= '0';
led_B(6) <= '1';
end if;
if (led_R_in(8)='0' AND ((led_R_in(2)='0' AND led_R_in(5)='0') OR (led_R_in(4)='0' AND led_R_in(0)='0') OR (led_R_in(9)='0' AND led_R_in(10)='0'))) then
led_B(8) <= '0';
led_R(8) <= '1';
led_G(8) <= '1';
else
led_R(8) <= led_R_in(8);
led_G(8) <= '0';
led_B(8) <= '1';
end if;
if (led_R_in(9)='0' AND ((led_R_in(1)='0' AND led_R_in(5)='0') OR (led_R_in(10)='0' AND led_R_in(8)='0'))) then
led_B(9) <= '0';
led_R(9) <= '1';
led_G(9) <= '1';
else
led_R(9) <= led_R_in(9);
led_G(9) <= '0';
led_B(9) <= '1';
end if;
if (led_R_in(10)='0' AND ((led_R_in(9)='0' AND led_R_in(8)='0') OR (led_R_in(5)='0' AND led_R_in(0)='0') OR (led_R_in(6)='0' AND led_R_in(2)='0'))) then
led_B(10) <= '0';
led_R(10) <= '1';
led_G(10) <= '1';
else
led_R(10) <= led_R_in(10);
led_G(10) <= '0';
led_B(10) <= '1';
end if;
END PROCESS;
PROCESS -- executes at the beginning (when is equal to "00") and changes its value every 10 ms
BEGIN
counter <= counter + "01"; -- there is an intended combinational loop here, so that it does this forever changing the row.
WAIT for 10 ms;
END PROCESS;
PROCESS (counter) -- executes at the beginning (when is equal to "00") and when counter changes (every 10 ms)
BEGIN
CASE counter IS
WHEN "00" => row <= "1000";
WHEN "01" => row <= "0100";
WHEN "10" => row <= "0010";
WHEN OTHERS => Null; -- for avoiding the automatic generation of latches due to non existing assignments. although it could also be row <= "0001"
END CASE;
END PROCESS;
END arc1;
why is it not working with the behaviour that I want?
I am new in VHDL. I try to create train ticket machine using vhdl. It have 3 destination and all destination have fee. When user insert money with same of fee, ticket will out and no change but if user enter extra money than fee, ticket will out also with change.When i run the simulation all output does not appear correctly but only come out with uuu. Anybody can help me with my code below, please.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity trainticket_machine is
PORT( Clock,Reset,Cancel : IN STD_LOGIC;
RM1,RM2,RM5 : IN STD_LOGIC;
KL_station,Mid_station,Klang_station : IN STD_LOGIC;
Ticket : OUT STD_LOGIC;
Change,Retrn : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
Money_sum : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end trainticket_machine;
architecture Behavioral of trainticket_machine is
TYPE state IS (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,Cancl,waiting1,waiting2,waiting3,KL_Ticket,Mid_Ticket,Shah_Ticket);
SIGNAL p_state,Train_state: STATE;
BEGIN
PROCESS(Reset,Clock)
BEGIN
IF (Reset = '1') THEN
p_state <= S0;
Ticket <= '0';
Retrn <= "0000";
Money_sum <= "ZZZZ";
ELSIF (Clock'EVENT AND Clock = '1') THEN
p_state <= Train_state;
END IF;
END PROCESS;
PROCESS (p_state,Cancel,RM1,RM2,RM5,KL_station,Mid_station,Klang_station)
BEGIN
CASE p_state IS
WHEN S0 =>
Money_sum <= "0000";
Change <= "0000";
IF (KL_station = '1') THEN Train_state <= waiting1;
ELSIF(Mid_station = '1') THEN Train_state <= waiting2;
ELSIF(Klang_station = '1') THEN Train_state <= waiting3;
ELSE Train_state <= S0;
END IF;
WHEN waiting1 =>
Ticket <= '0';
Change <= "0000";
IF (RM1 = '1') THEN Train_state <= S1;
ELSIF (RM2 = '1') THEN Train_state <= S2;
ELSIF (RM5 = '1') THEN Train_state <= S3;
ELSIF (Money_sum >= 2) THEN train_state <= KL_Ticket;
ELSIF (Cancel = '1') THEN Train_state <= Cancl;
ELSE Train_state <= waiting1;
END IF;
WHEN waiting2 =>
Ticket <= '0';
Change <= "0000";
IF (RM1 = '1') THEN Train_state <= S4;
ELSIF (RM2 = '1') THEN Train_state <= S5;
ELSIF (RM5 = '1') THEN Train_state <= S6;
ELSIF (Money_sum >= 4) THEN train_state <= Mid_Ticket;
ELSIF (Cancel = '1') THEN Train_state <= Cancl;
ELSE Train_state <= waiting2;
END IF;
WHEN waiting3 =>
Ticket <= '0';
Change <= "0000";
IF (RM1 = '1') THEN Train_state <= S7;
ELSIF (RM2 = '1') THEN Train_state <= S8;
ELSIF (RM5 = '1') THEN Train_state <= S9;
ELSIF (Money_sum >= 6) THEN train_state <= Shah_Ticket;
ELSIF (Cancel = '1') THEN Train_state <= Cancl;
END IF;
WHEN S1 =>
IF (RM1 <= '1' AND RM2 <= '0' AND RM5 <= '0') THEN
Ticket <= '0';
Change <= "0000";
Money_sum <= Money_sum + 1;
ELSE Train_state <= waiting1;
END IF;
WHEN S2 =>
IF (RM1 <= '1' AND RM2 <= '1' AND RM5 <= '0') THEN
Ticket <= '1';
Change <= "0000";
Money_sum <= Money_sum + 2;
ELSE Train_state <= waiting1;
END IF;
WHEN S3 =>
IF (RM1 <= '0' AND RM2 <= '0' AND RM5 <= '1') THEN
Ticket <= '1';
Change <= "0001";
Money_sum <= Money_sum + 5;
ELSE Train_state <= waiting1;
END IF;
WHEN S4 =>
IF (RM1 <= '1' AND RM2 <= '0' AND RM5 <= '0') THEN
Ticket <= '0';
Change <= "0000";
Money_sum <= Money_sum + 1;
ELSE Train_state <= waiting2;
END IF;
WHEN S5 =>
IF (RM1 <= '0' AND RM2 <= '1' AND RM5 <= '0') THEN
Ticket <= '0';
Change <= "0000";
Money_sum <= Money_sum + 2;
ELSE Train_state <= waiting2;
END IF;
WHEN S6 =>
IF (RM1 <= '0' AND RM2 <= '0' AND RM5 <= '1') THEN
Ticket <= '0';
Change <= "0001";
Money_sum <= Money_sum + 5;
ELSE Train_state <= waiting2;
END IF;
WHEN S7 =>
IF (RM1 <= '1' AND RM2 <= '0' AND RM5 <= '0') THEN
Ticket <= '0';
Change <= "0000";
Money_sum <= Money_sum + 1;
ELSE Train_state <= waiting3;
END IF;
WHEN S8 =>
IF (RM1 <= '0' AND RM2 <= '1' AND RM5 <= '0') THEN
Ticket <= '0';
Change <= "0000";
Money_sum <= Money_sum + 2;
ELSE Train_state <= waiting3;
END IF;
WHEN S9 =>
IF (RM1 <= '0' AND RM2 <= '0' AND RM5 <= '1') THEN
Ticket <= '0';
Change <= "0000";
Money_sum <= Money_sum + 5;
ELSE Train_state <= waiting3;
END IF;
WHEN KL_Ticket =>
Ticket <= '1';
Change <= Money_sum - 2;
Train_state <= waiting1;
WHEN Mid_Ticket =>
Ticket <= '1';
Change <= Money_sum - 4;
Train_state <= waiting2;
WHEN Shah_Ticket =>
Ticket <= '1';
Change <= Money_sum - 6;
Train_state <= waiting3;
WHEN Cancl =>
IF (Cancel <= '1') THEN
Retrn <= Money_sum;
ELSE Train_state <= S0;
END IF;
END CASE;
END PROCESS;
end Behavioral;
------------------------------simulation----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
ENTITY trainticket_machine_tb IS
END trainticket_machine_tb;
ARCHITECTURE behavior OF trainticket_machine_tb IS
Signal Clock,Reset,Cancel,RM1,RM2,RM5,KL_station,Mid_station,Klang_station : std_logic := '0';
Signal Ticket : std_logic ;
signal Change,Retrn,Money_sum : std_logic_vector(3 downto 0);
constant Clock_period : time := 10 ns;
BEGIN
uut: entity work.trainticket_machine PORT MAP (
Clock => Clock,
Reset => Reset,
Cancel => Cancel,
RM1 => RM1,
RM2 => RM2,
RM5 => RM5,
KL_station => KL_station,
Mid_station => Mid_station,
Klang_station => Klang_station,
Ticket => Ticket,
Change => Change,
Retrn => Retrn,
Money_sum => Money_sum
);
Clock_process :process
begin
Clock <= '0';
wait for Clock_period/2;
Clock <= '1';
wait for Clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for Clock_period*2;
Reset <= '1';
wait for Clock_period;
Reset <= '0';
wait for Clock_period;
Cancel <= '1';
wait for Clock_period;
Cancel <= '0';
wait for Clock_period;
KL_station <= '1';
wait for Clock_period;
KL_station <= '0';
wait for Clock_period;
Mid_station <= '1';
wait for Clock_period;
Mid_station <= '0';
wait for Clock_period;
Klang_station <= '1';
wait for Clock_period;
Klang_station <= '0';
wait for Clock_period;
RM1 <= '1';
wait for Clock_period;
RM1 <= '0';
wait for Clock_period;
RM2 <= '1';
wait for Clock_period;
RM2 <= '0';
wait for Clock_period;
RM5 <= '1';
wait for Clock_period;
RM5 <= '0';
wait for Clock_period;
wait;
end process;
END;
Starting with the first problem you describe: since you are seeing only 'U's, maybe your outputs were never assigned any value. Did you remember to force Reset to '1' in the beginning of the simulation?
Now let's take a look at the state machine logic itself, which has many problems. First thing: you should differentiate between combinational logic and registered state. By state I mean values that must be kept in registers of flip-flops, between the clock transitions.
This is important because for each process you will have to decide whether it is combinational or registered. If the process is registered, it must be sensitive to your clock. If the process is combinational, it cannot have any statements that woud imply keeping state information.
So the first suggestion is to go through your code, and decide the nature of each process you have. You may have to create a few more processes, it's ok. From your code, it looks like the signal money_sum is state information, and therefore it should be updated on the rising edge of clock.
The second suggestion is: if you have an output that depends only on the current state (maybe your signal ticket), you need to assign a value to this signal on every condition of your case statement. Try removing the line Ticket <= '0'; from your first process and see what happens.
Third, please use more descriptive names for your states and signals, it is really hard to understand what is going on from names like S0, S1, S2, RM1, RM2, and RM5.
Finally, it would be really helpful to have some assertions in your testbench code. For instance, after every wait for Clock_period;, you could check your outputs to make sure they match what you expected:
Reset <= '1';
wait for Clock_period;
assert ticket = '0' report "Wrong value for 'ticket' after reset";
assert change = "0000" report "Wrong value for 'change' after reset";
assert retrn = "0000" report "Wrong value for 'retrn' after reset";
assert money_sum = "0000" report "Wrong value for 'money_sum' after reset";