Error: Libero SoC 11.9 VHDL compile "A homograph of hread is already declared in the region" - vhdl

Question

I am a novice at VHDL. Im getting the following compile errors:
A homograph of hread is already in the region
A homograph of hread is already in the region
A homograph of hwrite is already in the region
The location of the errors appear as if Libero
compilation is not telling the difference between Std_ULogic_Vector and Std_Logic_Vector. Any insight is helpful.
Slyswine
--pragma translate_off
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_on
package StdIO is
--pragma translate_off
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector;
variable GOOD: out Boolean);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector);
procedure HRead(
variable L: inout Line;
variable VALUE: out bit_vector);
procedure HRead( -- "Error occurs on this line"
variable L: inout Line;
variable VALUE: out Std_Logic_Vector;
variable GOOD: out Boolean);
procedure HRead( -- "and this line"
variable L: inout Line;
variable VALUE: out Std_Logic_Vector);
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_ULogic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
procedure HWrite( -- "and this line"
variable L: inout Line;
constant VALUE: in Std_Logic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
procedure Write(
variable L: inout Line;
constant VALUE: in Std_ULogic;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
--pragma translate_on
end package StdIO;

Answer 1

The TL;DR answer
All of these subprogram declarations are already covered in package std_logic_1164 for an IEEE Std 1076-2008 revision compliant tool. Also in n -2008 STD_LOGIC_VECTOR is a subtype of STD_ULOGIC_VECTOR, meaning the base type (STD_ULOGIC_VECTOR) is the same and they errors are homographs (which aren't allowed here in the same declarative region).
When using -2008 package StdIO (it's declaration shown here) isn't needed unless there are behavioral differences in a subprogram specification.
The package declaration would analyze correctly in a tool compliant to an earlier revision of the VHDL standard because STD_LOGIC_VECTOR is declared as a separate type in package std_logic_1164.
The long answer
The Errors
12.3 Visibility
... Each of two declarations is said to be a homograph of the other if and only if both declarations have the same designator, and they denote different named entities, and either overloading is allowed for at most one of the two, or overloading is allowed for both declarations and they have the same parameter and result type profile (see 4.5.1).
4.5 Subprogram overloading
4.5.1 General
Two formal parameter lists are said to have the same parameter type profile if and only if they have the same number of parameters, and if at each parameter position the corresponding parameters have the same base type. Two subprograms are said to have the same parameter and result type profile if and only if both have the same parameter type profile, and if either both are functions with the same result base type or neither of the two is a function.
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector;
variable GOOD: out Boolean);
and
procedure HRead( -- "Error occurs on this line"
variable L: inout Line;
variable VALUE: out Std_Logic_Vector;
variable GOOD: out Boolean);
are being considered homographs as are
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector);
and
procedure HRead( -- "and this line"
variable L: inout Line;
variable VALUE: out Std_Logic_Vector);
As well as
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_ULogic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
and
procedure HWrite( -- "and this line"
variable L: inout Line;
constant VALUE: in Std_Logic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
12.3 Visibility
...
Two declarations that occur immediately within the same declarative region, other than the declarative region of a block implied by a component instantiation or the declarative region of a generic-mapped package or subprogram equivalent to a package instance or a subprogram instance, shall not be homographs, unless exactly one of them is the implicit declaration of a predefined operation or is an implicit alias of such an implicit declaration. In such cases, a predefined operation or alias thereof is always hidden by the other homograph. Where hidden in this manner, an implicit declaration is hidden within the entire scope of the other declaration (regardless of which declaration occurs first); the implicit declaration is visible neither by selection nor directly. For a declarative region of a block implied by a component instantiation or the declarative region of a generic-mapped package or subprogram equivalent to a package instance or a subprogram instance, the rules of this paragraph are applied to the corresponding entity declaration, component declaration, uninstantiated package declaration, or uninstantiated subprogram declaration, as appropriate.
...
To avoid a rathole HREAD and HWRITE are explicitly declared in package std_logic_1164 (-2008) and
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector;
variable GOOD: out Boolean);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector);
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_ULogic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
are legal overloads of the procedures declared in -2008 package std_logic_1164. (These are the declarations for which following illegal homographs are found. They aren't implicitly declared or aliases. These declarations are not found in earlier revision versions of package std_logic_1164. The implication is none of these declarations may be necessary in the OP's package StdIO.)
And these are errors:
1.3 Structure and terminology of this standard
1.3.1 General
In this document, the word shall is used to indicate a mandatory requirement. The word should is used to indicate a recommendation. The word may is used to indicate a permissible action. The word can is used for statements of possibility and capability.
1.3.3 Semantic description
The meaning and restrictions of a particular construct are described with a set of narrative rules immediately following the syntactic productions. In these rules, an italicized term indicates the definition of that term, and identifiers appearing entirely in uppercase letters refer to definitions in package STANDARD (see 16.3).
The following terms are used in these semantic descriptions with the following meanings:
erroneous: The condition described represents an ill-formed description; however, implementations are not required to detect and report this condition. Conditions are deemed erroneous only when it is impossible in general to detect the condition during the processing of the language.
error: The condition described represents an ill-formed description; implementations are required to detect the condition and report an error to the user of the tool.
illegal: A synonym for “error.”
legal: The condition described represents a well-formed description.
The homograph subprogram declarations produce errors, not meeting a semantic requirement that is mandatory (the use of shall in 12.3 above).
Why they're homographs is based on the use of IEEE Std 1076-2008 compliant VHDL tool where in IEEE package std_logic_1164 STD_LOGIC_VECTOR is a subtype of STD_ULOGIC_VECTOR:
subtype STD_LOGIC_VECTOR is (resolved) STD_ULOGIC_VECTOR;
Note for homograph procedure declarations the interface objects of the form:
6.5.2 Interface object declarations
interface_constant_declaration ::=
[ constant ] identifier_list : [ in ] subtype_indication [ := static_expression ]
interface_variable_declaration ::=
[ variable ] identifier_list : [ mode ] subtype_indication [ := static_expression ]
whose subtype indication type marks:
6.3 Subtype declarations
subtype_indication ::=
[ resolution_indication ] type_mark [ constraint ]
..
type_mark ::=
type_name
| subtype_name
have the same base type:
6.3 Subtype declarations
...
A type mark denotes a type or a subtype. If a type mark is the name of a type, the type mark denotes this type and also the corresponding unconstrained subtype. The base type of a type mark is, by definition, the base type of the type or subtype denoted by the type mark.
...
have the same parameter type profile (4.5.1), and the procedure declarations are homographs.
4.5 Subprogram overloading
4.5.1 General
...
A given subprogram designator can be used to designate multiple subprograms. The subprogram designator is then said to be overloaded; the designated subprograms are also said to be overloaded and to overload each other. If two subprograms overload each other, one of them can hide the other only if both subprograms have the same parameter and result type profile.
A call to an overloaded subprogram is ambiguous (and therefore is an error) if the name of the subprogram, the number of parameter associations, the types and order of the actual parameters, the names of the formal parameters (if named associations are used), and the result type (for functions) are not sufficient to identify exactly one (overloaded) subprogram.
Solutions
First you could use a tool compatible with an earlier revision of the VHDL standard. Prior to -2008 the std_ulogic_vector and std_logic_vector were two separate types.
Second you could delete the 'duplicate' declarations with std_logic_vector parameters and presumably any matching subprogram specifications in the package body while using -2008 compliant design specifications and tools. Potentially none of this package (as seen from it's declaration) is needed with -2008 unless there is some behavior found for any of it's subprogram specifications not provided in -2008 package std_logic_1164. If there's no differentiation in behavior the package StdIO isn't needed whatsoever, all it's procedures are declared in -2008 package std_logic_1164. (You may get a glimmer of why STD_LOGIC_VECTOR is a subtype of STD_ULOGIC_VECTOR in -2008, it reduces the number of subprogram declarations and specifications drammatically.)
Resources
The source for the -2008 package bodies as well as earlier package bodies can be found here if not made available in your tool implementation. (Respectively 1076-2008_downloads.zip and 1076.2-1996_downloads.zip). For purposes of these errors only the declarations for STD_LOGIC_VECTOR in package std_logic_1164 need be considered (1076-2008_downloads/1076-2008_machine-readable/ieee/std_logic_1164.vhdl and 1076.2-1996_downloads/std_logic_1164.vhdl).
Other items
You don't need the library clause for std nor the use clause for std.standard in the context clause of package StdIO.
See IEEE Std 1076-2008:
13.2 Design libraries.
...
Every design unit except a context declaration and package STANDARD is assumed to contain the following implicit context items as part of its context clause:
library STD, WORK; use STD.STANDARD.all;