4-bit ALU using VHDL showing error: no function declarations for operator "+" ("-", "*",and "/") - vhdl

Question

When I compile this code using ghdl it produces errors.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
generic ( constant N: natural := 1 );
port( a,b : in std_logic_vector(3 downto 0);
sel : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0);
x: out std_logic_vector(7 downto 0);
cout : out std_logic);
end alu;
architecture behavioral of alu is
signal rslt : std_logic_vector(3 downto 0);
signal tmp : std_logic_vector(4 downto 0);
begin
process(a,b,sel)
begin
case sel is
when "0000"=>
rslt<= a + b; -- Line 33
when "0001"=>
rslt<= a - b; -- Line 35
when "0010"=>
x<= (unsigned(a)) * (unsigned(b)); -- Line 37
when "0011"=>
x<=(unsigned(a)) / (unsigned(b)); -- Line 39
when "0100"=>
rslt<=std_logic_vector(unsigned(a) sll N);
when "0101"=>
rslt<=std_logic_vector(unsigned(a) srl N);
when "0110"=>
rslt<=std_logic_vector(unsigned(a) rol N);
when "0111"=>
rslt<=std_logic_vector(unsigned(a) ror N);
when "1000"=>
rslt<= a and b;
when "1001"=>
rslt<= a or b;
when "1010"=>
rslt<= a xor b;
when "1011"=>
rslt<= a xnor b;
when "1100"=>
rslt<= a nand b;
when "1101"=>
rslt<= a nor b;
when "1110"=>
if (a > b) then
rslt<= "0001";
else
rslt<="0000";
end if;
when "1111"=>
if (a = b)then
rslt<="0001";
else
rslt<="0000";
end if;
when others=>
rslt<= "0000";
end case;
end process;
y<=rslt;
tmp<= ('0' & a) + ('0' & b); -- Line 78
cout<=tmp(4);
end behavioral;
ghdl -a alu.vhdl
alu.vhdl:33:19:error: no function declarations for operator "+"
alu.vhdl:35:19:error: no function declarations for operator "-"
alu.vhdl:37:29:error: no function declarations for operator "*"
alu.vhdl:39:28:error: no function declarations for operator "/"
alu.vhdl:78:17:error: no function declarations for operator "+"
When using unsigned arithmetic, How can I make these operators available?

Answer 1

Welcome on Stackoverflow. You are apparently not very familiar with typed languages. VHDL is a typed language in which variables, signals, constants have a type, like bit, integer, std_logic_vector(3 downto 0) or unsigned(3 downto 0). And these types define what can be done and what cannot.
By default you cannot add two std_logic_vector(3 downto 0) and get a result that is also a std_logic_vector(3 downto 0). This is what you try to do with rslt<= a + b;. The compiler simply tells you that no such "+" operator is visible.
Same for rslt<= a - b; with the "-" operator.
x<= (unsigned(a)) * (unsigned(b)); is slightly better because you did not try to multiply two std_logic_vector(3 downto 0). You converted them to unsigned(3 downto 0) instead. Good choice because the ieee.numeric_std package overloads the "*" operator for the unsigned(...) types. Unfortunately you try to assign the result to a std_logic_vector(7 downto 0) while the ieee.numeric_std."*" operator returns a unsigned(7 downto 0). So, here again, the compiler complains that it does not find a suitable "*" operator. Note: the parentheses are not needed. You could simply write unsigned(a) * unsigned(b).
The other errors are left unexplained as an exercise.
I suggest that you read again your VHDL book and understand what types are, what kind of operations are defined by default on std_logic_vector(...) and unsigned(...) types and what extra operations are defined on the same types by the two packages you declare (ieee.std_logic_1164 and ieee.numeric_std).