I can't get what's wrong with my makefile:
DIST_PATH = ../dist/libs
BUILD_PATH = ../build
MKDIR_P = mkdir -p
.PHONY: all
SHELL = /bin/sh
CC = gcc
FLAGS = -std=gnu99
CFLAGS = -fPIC -pedantic -Wall -Werror
LDFLAGS = -shared
LOG_SRCS = $(shell echo log/*.c)
LOG_HEADERS = $(shell echo log/*.h)
LOG_OBJS = $(addprefix $(BUILD_PATH)/, $(notdir $(LOG_SRCS:.c=.o)))
LOG_TARGET = $(DIST_PATH)/liblog.so
all: dirs $(LOG_TARGET)
dirs :
$(MKDIR_P) $(DIST_PATH)
$(MKDIR_P) $(BUILD_PATH)
$(LOG_TARGET) : $(LOG_OBJS)
$(CC) $(FLAGS) $(CFLAGS) -o $# $(LDFLAGS)
I need to build a shared library from sources in log/ folder to ../dist/libs and put obj file in ../build but I am getting the error:
make: *** No rule to make target '../build/log.o', needed by '../dist/libs/liblog.so'. Stop.
P.S. I know there are many similar questions but I couldn't get from these questions how to resolve my problem.
The problem is that the source and object files are supposed to be placed in different directories, and there's no implicit rule for that.
You need to add a rule for how to translate a source file to an object file:
$(BUILD_PATH)/%.o: log/%.c
Now make knows how to create the object files from the source files.
There's another problem though:
$(LOG_TARGET) : $(LOG_OBJS)
$(CC) $(FLAGS) $(CFLAGS) -o $# $(LDFLAGS)
The command doesn't list any input files, you need to add all the object files to be linked:
$(LOG_TARGET) : $(LOG_OBJS)
$(CC) $(FLAGS) $(CFLAGS) -o $# $^ $(LDFLAGS)
# ^^
# List of all "prerequisites" (object files) to be linked
Related
I'm trying to link a .h file from a folder into a Makefile using a .mk file. Folder with .h file (include) is in the same folder as Makefile.
When I run from terminal: make memory.o or make memory.o PLATFORM=MSP432 I get the following error
make: *** No rule to make target '-I./include', needed by 'memory.o'. Stop.
My .mk folder looks like this:
# Add your Source files to this variable
SOURCES = \
./main.c \
./memory.c
# Add your include paths to this variable
INCLUDES =-I./include
My Make file looks like this:
include sources.mk
# Platform Overrides
PLATFORM =
# Architectures Specific Flags
LINKER_FILE = msp432p401r.lds
CPU = cortex-m0plus
ARCH = thumb
SPECS = nosys.specs
# Compiler Flags and Defines
CC = arm-none-eabi-gcc
LD = arm-none-eabi-ld
TARGET= c1m2
LDFLAGS = -Wl, -Map=$(TARGET).map -T $(LINKER_FILE)
CFLAGS = -Wall -Werror -g -O0 -std=c99 -mcpu=$(CPU) -m$(ARCH) --specs=$(SPECS)
CPPFLAGs =
ifeq ($(PLATFORM),MSP)
CPU=cortex-m4
CC=arm-none-eabi-gcc
endif
ifeq ($(PLATFORM),HOST)
CC=gcc
endif
OBJS = $(SOURCES:.c=.o)
%.o : %.c $(INCLUDES)
$(CC) -c $< $(CFLAGS) -o $#
.PHONY: build
build: all
.PHONY: all
all: $(TARGET).out
$(TARGET).out: $(OBJS) $(INCLUDES)
$(CC) $(OBJS) $(CFLAGS) $(LDFLAGS) -o $#
.PHONY: clean
clean:
rm -f $(OBJS) $(TARGET).out $(TARGET).map
Can anybody help?
You shouldn't put $(INCLUDES) as a prerequisite of your .o file. This is not right:
%.o : %.c $(INCLUDES)
$(CC) -c $< $(CFLAGS) -o $#
INCLUDES contains options that need to be passed to the compiler (-I...). Prerequisites of targets need to be files that are used during the build. I suppose you want this:
%.o : %.c
$(CC) -c $< $(CFLAGS) $(INCLUDES) -o $#
I have a recipe in my makefile that relies on several object files. I would like it to simply link the them, but they are always recompiling.
I've googled around and found information I did not know(marked with #) and changed it a bit, but the problem persisted.
I am led to believe make expects the name of the recipe be the name of the file, and I am failing to accomplish that. The problem is I do not what else to try and fix this. I would appreciate any help
CC = g++
#.PHONY: sfml-app
LIBS = -lsfml-graphics -lsfml-window -lsfml-system
APPLICATION = sfml-app
INCLUDE_DIR = -I include/
SOURCE_DIR = source
OUTPUT_DIR = bin
SOURCES = $(wildcard $(SOURCE_DIR)/*.cpp)
OBJECTS = $(notdir $(patsubst %.cpp, %.o, $(SOURCES)))
#$(OUTPUT_DIR)/$(APPLICATION): $(OBJECTS)
#bin/sfml-app: $(OBJECTS)
#sfml-app: $(OBJECTS)
#$(APPLICATION): $(OBJECTS)
$(CC) $(OUTPUT_DIR)/*.o $(LIBS) -o $(OUTPUT_DIR)/$(APPLICATION)
%.o: $(SOURCE_DIR)/%.cpp
$(CC) -c $< $(INCLUDE_DIR) -o $(OUTPUT_DIR)/$#
clean:
rm $(OUTPUT_DIR)/*
print-% : ; #echo $* = $($*)
This rule doesn't create the file it promises to:
%.o: $(SOURCE_DIR)/%.cpp
$(CC) -c $< $(INCLUDE_DIR) -o $(OUTPUT_DIR)/$#
See that -o $(OUTPUT_DIR)/$#? That's instructing the compiler to create a file in $(OUTPUT_DIR) instead of in the working directory.
If you really want your object files to go in $(OUTPUT_DIR), you need to make sure that your rule indicates that:
$(OUTPUT_DIR)/%.o: $(SOURCE_DIR)/%.cpp
$(CC) -c $< $(INCLUDE_DIR) -o $#
Or better, to act like the standard %.o: %.c rule (which will include CFLAGS etc):
$(OUTPUT_DIR)/%.o: $(SOURCE_DIR)/%.cpp
$(COMPILE.c) $(OUTPUT_OPTION) $<
I note your input files are named *.cpp - usually, that convention is for C++ files (i.e. to be compiled with $(COMPILE.cc), which will invoke $(CXX) rather than $(CC)). Check that you've not mixed up your C and C++ sources!
I just began learning about GNU make yesterday. As the title says, it appears that the % sign in my Makefile is not being recognised. Or perhaps I am using it the wrong way. Can someone enlighten me?
CXX = clang++
EXE = Invaders
SDL = -F./lib
LDFLAGS = $(SDL)
SRCDIR = src
OBJDIR = obj
SRC = $(SRCDIR)/main.cpp $(wildcard $(SRCDIR)/util/*.cpp) $(wildcard $(SRCDIR)/misc/*.cpp)
OBJ = $(patsubst $(SRCDIR)/%.cpp,$(OBJDIR)/%.o,$(SRC))
all: $(EXE)
$(EXE): $(OBJ)
$(CXX) $(LDFLAGS) -o bin/$# $^
$(OBJDIR)/%.o: $(SRCDIR)/%.cpp $(SRCDIR)/%.h
$(CXX) -c -o $# $<
Console output:
make: *** No rule to make target `obj/main.o', needed by `Invaders'. Stop.
Tree view of my entire project with directories /obj and /src expanded
Thanks!
This rule:
$(OBJDIR)/%.o: $(SRCDIR)/%.cpp $(SRCDIR)/%.h
$(CXX) -c -o $# $<
does not fit obj/main.o, because there is no src/main.h.
(Also, please put the necessary information in the body of the question, don't rely on a link to an image.)
I am trying to update my Makefile to support building a binary of my project, and a binary of some Unit Tests.
My directory structure is the following
|-code/
|--|--src/
|--|--inc/
|
|-tests/
|--|--src/
|--|--inc/
My makefile compiles the binary from code well, but is having some issues with the test. The test folder contains some unit test that tests some classes in code/src/. I have a file main.cpp in code/src/ that contains the main() function, and also another file, called test.cpp in tests/src that contains its own main() function.
This led me to this complicated Makefile:
CC = g++
FLAGS = -g -c -Wall
INCLUDEDIR = -Icode/inc -Itests/inc
BUILDDIR = build
SOURCEDIR = code/src
SOURCES = $(wildcard $(addsuffix /*.cpp,$(SOURCEDIR)))
TEMP_OBJ = $(SOURCES:%.cpp=%.o)
NOT_DIR = $(notdir $(TEMP_OBJ))
OBJECTS = $(addprefix $(BUILDDIR)/, $(NOT_DIR))
TEST_DIR = tests/src
TEST_SOURCES = $(wildcard $(addsuffix /*.cpp,$(TEST_DIR)))
TEST_TEMP_OBJ = $(TEST_SOURCES:%.cpp=%.o)
TEST_NOT_DIR = $(notdir $(TEST_TEMP_OBJ))
TEST_OBJECTS = $(addprefix $(BUILDDIR)/, $(TEST_NOT_DIR))
EXECUTABLE = Client
TEST_EXECUTABLE = TestUnit
all: $(BUILDDIR) $(BUILDDIR)/$(EXECUTABLE) $(BUILDDIR)/$(TEST_EXECUTABLE)
$(BUILDDIR):
mkdir -p $#
$(BUILDDIR)/$(EXECUTABLE): $(OBJECTS)
$(CC) $^ -o $#
$(BUILDDIR)/%.o : code/src/%.cpp
$(CC) $(FLAGS) $< $(INCLUDEDIR) -o $#
$(BUILDDIR)/$(TEST_EXECUTABLE): $(OBJECTS) $(TEST_OBJECTS)
#rm -f $(BUILDDIR)/main.o
$(CC) $^ -o $#
$(BUILDDIR)/%.o : tests/src/%.cpp
$(CC) $(FLAGS) $< $(INCLUDEDIR) -o $#
clean:
rm -rf $(BUILDDIR)
It fails with the error:
g++: error: build/main.o: No such file or directory
make: *** [build/TestUnit] Error 1
Which is because I have the line:
#rm -f $(BUILDDIR)/main.o
but otherwise I would get the error (there is main in main.cpp and test.cpp in code/src/ and tests/code/ respectively):
/tests/src/test.cpp:7: multiple definition of `main'
code/src/main.cpp:6: first defined here
collect2: error: ld returned 1 exit status
There is a lot of duplication in my Makefile, and I would love to get something more succinct that achieves the purpose of building 2 binaries from those 2 folders, although code is shared.
Any help would please be appreciated. Thank you very much!
There are a number of problems with this makefile.
First, there is no rule to build test object files, such as test.o. The only rule for building objects requires that the source be in code/src/; I don't know how you even get far enough to see a linker error.
Let's change the object rule to a static pattern rule:
$(OBJECTS) : $(BUILDDIR)/%.o : code/src/%.cpp
$(CC) $(FLAGS) $< $(INCLUDEDIR) -o $#
Then we can add an additional rule for the test objects:
$(TEST_OBJECTS) : $(BUILDDIR)/%.o : tests/src/%.cpp
$(CC) $(FLAGS) $< $(INCLUDEDIR) -o $#
(Never mind the redundancy for now-- we have to get it working first.)
Now we should see a linker error in this rule:
$(BUILDDIR)/$(TEST_EXECUTABLE): $(OBJECTS) $(TEST_OBJECTS)
...
In that list of prerequisites are two files, main.o and test.o fighting over who gets to define main(). We want test.o, so main.o must go:
$(BUILDDIR)/$(TEST_EXECUTABLE): $(filter-out build/main.o,$(OBJECTS)) $(TEST_OBJECTS)
...
Try this much and tell us the result. Once it's working we can slim it down.
following is my makefile. but It is not taking include path during build.
SHELL = /bin/sh
CC = g++
FLAGS =
CFLAGS = -fPIC
TARGET = my_bridge.so
INC=-I/my_custom_path/include/ -I/my_custom_path/include/linux
SOURCES = $(shell echo *.cpp)
HEADERS = $(shell echo *.h)
OBJECTS = $(SOURCES:.cpp=.o)
all: $(TARGET)
$(TARGET): $(OBJECTS)
$(CC) $(FLAGS) $(INC) $(CFLAGS) -o $(TARGET) $(OBJECTS)
When I build i get following line
g++ -c -o my_bridge.o my_bridge.cpp
Your $(TARGET): $(OBJECTS) rule tells make how to generate my_bridge.so out of my_bridge.o, but you haven't given a rule that explains how to make my_bridge.o in the first place. make relies thus on its implicit rules for that, which gives you the command that you see. You can either define your own rule to compile .cpp files, e.g.
%.o: %.cpp
$(CC) $(FLAGS) $(INC) $(CFLAGS) -o $# $<
or put your include directive in $(CXXFLAGS), which is used by make's default rule (see https://www.gnu.org/software/make/manual/html_node/Catalogue-of-Rules.html#Catalogue-of-Rules)