What did I do wrong with the selected signal assignment in my VHDL code?
with s select x <= a when (s = '1')
else y <= a when (s = '0');
I also tried this:
with s select x <= a when '1';
with s select y <= a when '0';
It's not completly clear what you want to do. From what you showed us, it seems to me that you want to create a demux controlled by signal s (1 input, 2 outputs), where x <= a when s='1' and y <= a when s='0'
The use of select should be done in cases when you want to create a mux (n inputs, 1 output). That is, the opposite of a demux!
I would recommend you to use a simple if statement to create a demux.
Example:
if s='1' then x <= a; else y <= a; end if;
Related
It might be a stupid question...
I want to make a de-multiplexer with one input: a , a byte and two outputs, x and y(also bytes).
there is also a signal input : s
The de-multiplexer should work with the selected signal assignment.
Whenever s is 1, x should be the value of a. When s is 0, the value of y should be the value of a.
with s select x <= a when '1';
with s select y <= a when '0';
when i put it in a process like this:
p1 : process (s,a)
with s select x <= a when '1';
with s select y <= a when '0';
end process;
I made a testbench and used it to test my dmux, when i trie to run it, it says that i didn't use al possibilities, but I did? Right?
Can anyone help me?
Thanks in advance
I'm writing a design in VHDL and after synthesis I observed that the number of multiplexers (dedicated) used is high. My code has a lot of if-else staments, so it seems logical.
But I wanna know if it is possible to implement if-else (or similar staments) in another way to reduce the number of multiplixers resources used.
Thanks!
You can try to use simple logic elements like and or or. For example:
if (a and b) = '1' then
out_0 <= '1';
else
out_0 <= '0';
end if;
if (c or d) = '1' then
out_1 <= '1';
else
out_1 <= '0';
end if;
This is construction can be replaced with following:
out_0 <= a and b;
out_1 <= c or d;
And so on...
I have this code:
architecture Behavioral of BlockName is
signal t: std_logic;
signal c : std_logic_vector (1 downto 0);
begin
process (reset, clk) begin
if (reset = '1') then
t <= '0';
c <= (others=>'0');
elsif clk'event and clk='l' then
if (c = din) then
t <= NOT(t);
c <= (others=>'0');
else
c <= c + 1;
end if;
end if;
end process;
dout <= t;
end Behavioral;
This code's role is to divide the frequency when it gets input (clock + value) and outputs a divided frequency.
Now my questions:
What does this c <= (others=>'0'); mean ?
What value does t get here t <= NOT(t); ? the last t value? does the <= work as = ?
c <= (others=>'0'); is equivalent to c <= "00";
t <= not(t); assigns to t the opposite of the current value in t.
= is an equality comparison in VHDL.
<= is signal assignment in VHDL.
since 'C' is taken as a vector and to store every bit of it with zero 'c <= (others=>'0');' was used and the concept of blocking and non blocking signals is not present in VHDL. here '=' is used to compare and '<=' is used to assign the signal.
In the your code 't' is declared as a signal and a signal will be updated at the end of the every iteration of the process block. so in the statement 't <= NOT(t);' the value of the t is still the old value and will be updated at the end of the current simulation tick.
if(rising_edge(clk)) then
count := count + 1;
if count = 3 then
enable <= 1;
elsif count = 6 then
enable <= 0;
count := 0;
end if;
end if;
if enable = 0 then
a0i <= a_0;
boi <= b_0;
end if;
if enable = 1 then
a0i <= a_1;
boi <= b_1;
end if;
All are signals except the count. Value of a0i and boi should response as soon as enable becomes either 0 or 1. I tried using the variable. but it can not allow me to use out side the process.
I am getting the o/p as this. How ever I want to change the input as soon as enable signal change.
Put the last two if conditions in another process
Process(enable, a_0, b_0, a_1, b_1)
begin
If(enable = '0')THEN
a0i <= ...
....
ELSE
.....
END IF;
END PROCESS;
This process is sensitive to the enable signal so anytime there is a change in enable, independent of the clock, the statements will take effect immediately (asynchronously)
Solution 1: use 2 processes as blueprint mentioned.
Solution 2: use an internal variable.
process(clk)
variable count : natural range of 0 to 6 := 0;
variable enable_i : std_logic := '0';
begin
if(rising_edge(clk)) then
count := count + 1;
if count = 3 then
enable_i := '1';
elsif count = 6 then
enable_i := '0';
count := 0;
end if;
end if;
if enable = '0' then
a0i <= a_0;
boi <= b_0;
else
a0i <= a_1;
boi <= b_1;
end if;
enable <= enable_i;
end process;
Some hints:
Maybee, the type boolean is more suitable for your signal/variable enable_i
If enable_i is only used inside the process, then you can remove the conversion to enable
including the data path and multiplexers in a state machine (I assume this is a part of it) is not a good design choice.
You could also take these two equation below out from your process.
process(...)
[...]
if enable = 0 then
a0i <= a_0;
boi <= b_0;
end if;
if enable = 1 then
a0i <= a_1;
boi <= b_1;
end if;
end process
Then you cannot use the IF statement anymore, but you can use the WHEN statement :
a0i <= a_0 when enable = '0' else a_1;
boi <= b_0 when enable = '0' else b_1;
Note that in this case, the multiplexer will be after the latch. This could be important if you have timing issues on these signals.
From your simulation waveform, it looks to me like you failed to include enable, a_0, b_0, a_1, and b_1 in your sensitivity list, but I can't be sure because you didn't post the complete example. Because you test the values of the 5 mentioned signals outside of the if rising_edge(clk), they need to be included. The values are only updated on the falling edge of clk because, presuming that clk is the only thing in your sensitivity list, that is the next time the process is evaluated.
It should be otherwise functional as written, although you could use an else instead of a separate test for enable = 0 for a slight readability improvement. Synthesis usually ignores the sensitivity list (it just makes simulation more efficient) so it should already work if you were to synthesize.
I started with VHDL course for beginners a few days ago.
I’ve got a code (under) and I’m trying to understand what kind of circuit it shows and how the different steps are functioning.
I’ve been looking around fore a while now in the Internet but can’t really understand what it does? So I thought someone who now this might give me some explanations’? :.-)
I`m not sure but I think it is a type of an “adder” with a buffer? And the buffer is working with 2 bits (Cs-1 downto 0) however I don’t know what Cs means….in fact there is a lot of things in this code I don’t understand.
I would really appreciate if some one would take some time to help me understand the code in words.
entity asc is
generic (CS : integer := 8)
port (k, ars, srs, e, u: in std_logic;
r: buffer std_logic_vector(Cs-1 downto 0));
end asc;
architecture arch of asc is
begin
p1: process (ars, k) begin
if ars = ‘1’ then
r <= (others => ‘0’);
elsif (k’event and k=’1’) then
if srs=’1’ then
r <= (others) => ‘0’);
elsif (e = ‘1’ and u = ‘1’) then
r <= r + 1;
elsif (e = ‘1’ and u = ‘0’) then
r <= r - 1;
else
r <= r;
end if;
end if;
end process;
end arch;
I renamed the inputs and outputs of your entity with Sigasi HDT (and corrected some syntax errors) which should make a lot more clear your entity does. I did following renames:
k -> clock
ars -> asynchronous_reset
srs -> synchronous_reset
e -> enable
u -> count_up
r-> result
If enable is asserted and count_up is true, the result (r) will be incremented on a rising clock edge. If count_up is false, the result will be decremented if enable is true on a rising clock edge.
entity asc is
generic (resultWidth : integer := 8);
port (clock, asynchronous_reset, synchronous_reset, enable, count_up: in std_logic;
result: buffer std_logic_vector(resultWidth-1 downto 0)
);
end asc;
architecture arch of asc is
begin
p1: process (asynchronous_reset, clock) begin
if asynchronous_reset = '1' then
result <= (others => '0');
elsif (rising_edge(clock)) then
if synchronous_reset='1' then
result <= (others => '0');
elsif (enable = '1' and count_up = '1') then
result <= result + 1;
elsif (enable = '1' and count_up = '0') then
result <= result - 1;
else
result <= result;
end if;
end if;
end process;
end arch;
Be careful when using this code snippet:
This architecture seems to be using deprecated libraries: what does adding 1 to a std_logic_vector mean? Please use the signed datatype instead. This way it is predictable what will happen if you decrement zero.
This entity will not warn you for overflow