Issue with Makefile recipe for inputting object files - makefile

Question

I have a makefile, that I edited so that object files should go to a separate directory.
I edited the makefile and it is now doing what I wanted to, but during linker stage it is not working as expected because I am doing something wrong.
I have a sources file and makefile as shown below:
Sources File
TARGET = demo
SRC_DIR = modbus/ascii/ \
modbus/functions/ \
modbus/port/ \
modbus/rtu/ \
modbus/ \
./
INCLUDE_DIR = modbus/include/ \
modbus/port/ \
modbus/rtu \
modbus/ascii \
./
SOURCE = modbus/ascii/mbascii.c \
modbus/functions/mbfunccoils.c \
modbus/functions/mbfuncdiag.c \
modbus/functions/mbfuncdisc.c \
modbus/functions/mbfuncholding.c \
modbus/functions/mbfuncinput.c \
modbus/functions/mbfuncother.c \
modbus/functions/mbutils.c \
modbus/port/port.c \
modbus/port/portevent.c \
modbus/port/portserial.c \
modbus/port/porttimer.c \
modbus/rtu/mbcrc.c \
modbus/rtu/mbrtu.c \
modbus/mb.c \
demo.c \
startup_LPC17xx.c \
system_LPC17xx.c
Makefile
include ./sources
ARCH = arm-none-eabi
BUILD_DIR := build/objs
# Tool definitions
CC = $(ARCH)-gcc
LD = $(ARCH)-gcc
AR = $(ARCH)-ar
AS = $(ARCH)-as
CP = $(ARCH)-objcopy
OD = $(ARCH)-objdump
SIZE = $(ARCH)-size
RM = rm
Q = # #./quiet "$#"
# Flags
CFLAGS = -W -Wall -O0 --std=gnu99 -fgnu89-inline -mcpu=cortex-m3 -mthumb
CFLAGS += -ffunction-sections -fdata-sections
ASFLAGS =
LDFLAGS = -nostartfiles -specs=nosys.specs
CPFLAGS =
ODFLAGS = -x --syms
PRFLAGS ?=
# Source files
LINKER_SCRIPT = LPC17xx.ld
OBJS = $(SOURCE:.c=.o)
BUILD_OBJS := $(patsubst %,$(BUILD_DIR)/%,$(SOURCE:.c=.o))
OBJ_DIR := $(dir $(BUILD_OBJS))
INC_PARAMS = $(foreach d, $(INCLUDE_DIR), -I$d)
print-% : ; #echo $* = $($*)
.PHONY: all size clean nuke
all: $(TARGET).bin $(TARGET).hex
isp: $(TARGET).bin
# #./quiet $< cp $^ $(MBED_VOLUME)/
size: $(TARGET).elf
#$(SIZE) $<
%.hex: %.elf
$Q $(CP) $(CPFLAGS) -O ihex $< $*.hex
%.bin: %.elf
$Q $(CP) $(CPFLAGS) -O binary $< $*.bin
$(TARGET).elf: $(OBJS)
#touch $(#:.elf=.map)
$Q $(LD) -Xlinker -Map $(#:.elf=.map) $(LDFLAGS) -T $(LINKER_SCRIPT) $(BUILD_DIR)/$^ -o $#
$Q $(OD) $(ODFLAGS) $# > $(#:.elf=.dump)
#$(SIZE) $#
$(OBJS): %.o: %.c
mkdir -p $(dir $(BUILD_OBJS))
$Q $(CC) $(CFLAGS) $(INC_PARAMS) -c $< -o $(BUILD_DIR)/$#
.PHONY: clean
clean: CRUFT=$(shell find . -name '*.o' -o -name '*.d')
clean: ; rm -f $(CRUFT); rm -f *.elf *.hex *.bin *.dump *.map; rm -rf $(BUILD_DIR)/*
nuke: clean
-rm -f *.hex *.bin *.dump *.map
The issue is in line:
$Q $(LD) -Xlinker -Map $(#:.elf=.map) $(LDFLAGS) -T $(LINKER_SCRIPT) $(BUILD_DIR)/$^ -o $#
For which the output is:
arm-none-eabi-gcc -Xlinker -Map demo.map -nostartfiles -specs=nosys.specs -T LPC17xx.ld build/objs/modbus/ascii/mbascii.o modbus/functions/mbfunccoils.o modbus/functions/mbfuncdiag.o modbus/functions/mbfuncdisc.o modbus/functions/mbfuncholding.o modbus/functions/mbfuncinput.o modbus/functions/mbfuncother.o modbus/functions/mbutils.o modbus/port/port.o modbus/port/portevent.o modbus/port/portserial.o modbus/port/porttimer.o modbus/rtu/mbcrc.o modbus/rtu/mbrtu.o modbus/mb.o demo.o startup_LPC17xx.o system_LPC17xx.o -o demo.elf
The output command picks only the first object file from correct directory under build/objs.
Rest object file path doesn't have build/objs/.
Please anyone help me resolve this issue?

Answer 1

You are violating Mad Scientist's second rule of makefiles, and inviting more problems than you know.
Look at these rules (simplified):
$(TARGET).elf: $(OBJS)
$(LD) $(BUILD_DIR)/$^ -o $#
$(OBJS): %.o: %.c
$(CC) -c $< -o $(BUILD_DIR)/$#
Suppose the build directory is build/ and the object file is build/foo.o. The target of the second rule is foo.o, but what it actually builds is build/foo.o. Likewise, the first rule claims foo.o as a prerequisite, but it doesn't actually use foo.o, it uses build/foo.o These two errors cancel each other out, in a sense; Make succeeds in building the main target. But as you have found, it has trouble if there is more than one object file, because if the prerequisite list is foo.o bar.o, then
`$(BUILD_DIR)/$^`
expands to
build/foo.o bar.o
Also, Make will run the second rule even if build/foo.o exists and is up to date, and will fail to run it if foo.o exists. The target of a non-PHONY rule should be the name of the file it builds, and a non-PHONY prerequisite should be the name of a file whose existence is relevant:
$(TARGET).elf: $(BUILD_OBJS)
$(LD) $^ -o $#
$(BUILD_OBJS): $(BUILD_DIR)/%.o: %.c
$(CC) -c $< -o $#