I'm trying to convert an existing makefile for macOS to one that will run under mingw-W64 on Windows10 - makefile

This is the makefile for MacOS The source directory contains the source files plus the makefile and srclist.make file
# makefile for molex on macOS
OBJDIR = ../Objects
SRCDIR = ./Source
include srclist.make
FC = gfortran
FFLAGS = -x f77-cpp-input -ffixed-line-length-132 -fno-align-commons -I$(SRCDIR) -O3
OBJECTS = $(addprefix $(OBJDIR)/, $(addsuffix .o, $(basename $(SRCLIST)) ))
SOURCES = $(addprefix $(SRCDIR)/, $(SRCLIST) )
vpath %.f $(SRCDIR)
vpath %.inc $(SRCDIR)
$(OBJDIR)/%.o : %.f
$(FC) -c $(FFLAGS) $< -o $#
molex : $(OBJECTS)
$(FC) -o molex $^
.PHONY : clean
clean:
rm $(OBJDIR)/*.o
srclist.make contains a list of fortran and include files to converted to object code which are placed in a separate Objects folder
SRCLIST = \
molex.f \
background.f \
bnu.f \
charfns.f \
checkparam.f \
escape.f \
extrap.f \
fcn.f \
fdjac.f \
fmin.f \
funcv.f \
getfs.f \
idtrans.f \
initcoll.f \
initx.f \
intensity.f \
levpop.f \
lnsrch2.f \
loadmol.f \
lubksb.f \
ludcmp2.f \
newt3.f \
nextline.f \
output.f \
tau.f \
taudust.f \
Tex.f \
bug.inc \
collisions.inc \
constants.inc \
control.inc \
moldata.inc \
nlevmax.inc \
nmax.inc \
parameters.inc \
radiative.inc \
I've tried placing escape backslashes in the macOS makefile and ran in cmd prmpt with mingw32-make
the environmental Path is set as C:\msys2\mingw-w64\bin
the partly edited makefile follows
# makefile for molex on macOS
OBJDIR = ..\\Objects
SRCDIR = .\\Source
include srclist.make
FC = gfortran
FFLAGS = -x f77-cpp-input -ffixed-line-length-132 -fno-align-commons -I$(SRCDIR) -O3
#OBJECTS = $(addprefix $(OBJDIR)/, $(addsuffix .o, $(basename $(SRCLIST)) ))
OBJECTS = $(addprefix $(OBJDIR)\\, $(addsuffix .o, $(basename $(SRCLIST)) ))
SOURCES = $(addprefix $(SRCDIR)/, $(SRCLIST) )
vpath %.f $(SRCDIR)
vpath %.inc $(SRCDIR)
$(OBJDIR)\%.o : %.f
$(FC) -c $(FFLAGS) $< -o $#
molex : $(OBJECTS)
$(FC) -o molex $^
.PHONY : clean
clean:
del $(OBJDIR)/*.o
The cmd prompt output follows
D:\test_molex_ian\Source>mingw32-make -f makefile molex
mingw32-make: *** No rule to make target '..\\Objects\\molex.o', needed by 'molex'. Stop.
I would appreciate some guidance please

Related

makefile missing separator showing up when using modified makefile for macOS

I am trying to use the makefile for my work related to SPheno. I am on macOS. When I try to use the command "make Model=Scotogenic". it's showing "*** missing separator". I went through lot of forums and added tabs. when I tried to do it again , now it's showing "*** commands commence before first target" . I am using the default textedit in macOS. I am attaching both the code and screenshot. The terminal screenshot
Code:
# PreDef = -DGENERATIONMIXING -DONLYDOUBLE -DSEESAWIII
PreDef = -DGENERATIONMIXING -DONLYDOUBLE
# setting various paths
InDir = ../include
Mdir = ${InDir}
name = ../lib/libSPheno.a
#
# options for various compilers
#
# Intels ifort, default in optimized mode
F90 = ifort
comp = -c -O -module ${Mdir} -I${InDir}
LFlagsB = -O
# Intels ifort, debug modus
ifeq (${F90},ifortg)
F90 = ifort
comp = -c -g -module ${Mdir} -I${InDir}
LFlagsB = -g
endif
gfortran
ifeq (${F90},gfortran)
comp = -c -O -J${Mdir} -I${InDir}
LFlagsB = -O
endif
# g95
ifeq (${F90},g95)
comp = -c -O -fmod=${Mdir} -I${InDir}
LFlagsB = -O
endif
# Lahey F95 compiler
ifeq (${F90},lf95)
comp = -c -O -M ${Mdir} -I${InDir}
LFlagsB = -O
endif
# NAG f95/2003
ifeq (${F90},nagfor)
comp = -c -O -DONLYDOUBLE -mdir ${Mdir} -I${InDir}
LFlagsB = -O
endif
.SUFFIXES : .o .ps .f90 .F90 .a
bin/SPheno: ${name} SPheno4.o
${F90} -o SPheno ${LFlagsB} SPheno4.o ../lib/${name}
mv SPheno ../bin
${name}: ${name}(Control.o) ${name}(Mathematics.o) ${name}(RGEs.o) \
${name}(MathematicsQP.o) ${name}(LoopFunctions.o) ${name}(StandardModel.o) \
${name}(Model_Data.o) ${name}(Couplings.o) ${name}(SusyMasses.o) \
${name}(LoopCouplings.o) ${name}(DecayFunctions.o) \
${name}(SusyDecays.o) ${name}(ThreeBodyPhaseSpace.o) \
${name}(ThreeBodyPhaseSpaceS.o) ${name}(Chargino3.o) \
${name}(Gluino3.o) ${name}(Neutralino3.o) \
${name}(Stop3BodyDecays.o) ${name}(Slepton3Body.o) ${name}(BranchingRatios.o) \
${name}(EplusEminusProduction.o) ${name}(TwoLoopHiggsMass.o) \
${name}(LoopMasses.o) ${name}(SugraRuns.o) ${name}(Experiment.o) \
${name}(LowEnergy.o) ${name}(NMSSM_tools.o) ${name}(RPtools.o) \
${name}(LHC_observables.o) ${name}(InputOutput.o)
clean:
rm -f *.o *~ */*.o */*~
cleanall:
rm -f bin/SPheno4 lib/*.a *~ */*.o */*~ include/*
#
# Suffix rules
#
.f90.a:
${F90} ${comp} $<
ar -ruc $# $*.o
rm -f $*.o
.F90.a:
${F90} ${comp} ${PreDef} $<
ar -ruc $# $*.o
rm -f $*.o
.f90.o:
${F90} ${comp} $<
.f90.ps:
a2ps -o $*.ps $<
.h.ps:
a2ps -o $*.ps $<

Issue with Makefile recipe for inputting object files

I have a makefile, that I edited so that object files should go to a separate directory.
I edited the makefile and it is now doing what I wanted to, but during linker stage it is not working as expected because I am doing something wrong.
I have a sources file and makefile as shown below:
Sources File
TARGET = demo
SRC_DIR = modbus/ascii/ \
modbus/functions/ \
modbus/port/ \
modbus/rtu/ \
modbus/ \
./
INCLUDE_DIR = modbus/include/ \
modbus/port/ \
modbus/rtu \
modbus/ascii \
./
SOURCE = modbus/ascii/mbascii.c \
modbus/functions/mbfunccoils.c \
modbus/functions/mbfuncdiag.c \
modbus/functions/mbfuncdisc.c \
modbus/functions/mbfuncholding.c \
modbus/functions/mbfuncinput.c \
modbus/functions/mbfuncother.c \
modbus/functions/mbutils.c \
modbus/port/port.c \
modbus/port/portevent.c \
modbus/port/portserial.c \
modbus/port/porttimer.c \
modbus/rtu/mbcrc.c \
modbus/rtu/mbrtu.c \
modbus/mb.c \
demo.c \
startup_LPC17xx.c \
system_LPC17xx.c
Makefile
include ./sources
ARCH = arm-none-eabi
BUILD_DIR := build/objs
# Tool definitions
CC = $(ARCH)-gcc
LD = $(ARCH)-gcc
AR = $(ARCH)-ar
AS = $(ARCH)-as
CP = $(ARCH)-objcopy
OD = $(ARCH)-objdump
SIZE = $(ARCH)-size
RM = rm
Q = # #./quiet "$#"
# Flags
CFLAGS = -W -Wall -O0 --std=gnu99 -fgnu89-inline -mcpu=cortex-m3 -mthumb
CFLAGS += -ffunction-sections -fdata-sections
ASFLAGS =
LDFLAGS = -nostartfiles -specs=nosys.specs
CPFLAGS =
ODFLAGS = -x --syms
PRFLAGS ?=
# Source files
LINKER_SCRIPT = LPC17xx.ld
OBJS = $(SOURCE:.c=.o)
BUILD_OBJS := $(patsubst %,$(BUILD_DIR)/%,$(SOURCE:.c=.o))
OBJ_DIR := $(dir $(BUILD_OBJS))
INC_PARAMS = $(foreach d, $(INCLUDE_DIR), -I$d)
print-% : ; #echo $* = $($*)
.PHONY: all size clean nuke
all: $(TARGET).bin $(TARGET).hex
isp: $(TARGET).bin
# #./quiet $< cp $^ $(MBED_VOLUME)/
size: $(TARGET).elf
#$(SIZE) $<
%.hex: %.elf
$Q $(CP) $(CPFLAGS) -O ihex $< $*.hex
%.bin: %.elf
$Q $(CP) $(CPFLAGS) -O binary $< $*.bin
$(TARGET).elf: $(OBJS)
#touch $(#:.elf=.map)
$Q $(LD) -Xlinker -Map $(#:.elf=.map) $(LDFLAGS) -T $(LINKER_SCRIPT) $(BUILD_DIR)/$^ -o $#
$Q $(OD) $(ODFLAGS) $# > $(#:.elf=.dump)
#$(SIZE) $#
$(OBJS): %.o: %.c
mkdir -p $(dir $(BUILD_OBJS))
$Q $(CC) $(CFLAGS) $(INC_PARAMS) -c $< -o $(BUILD_DIR)/$#
.PHONY: clean
clean: CRUFT=$(shell find . -name '*.o' -o -name '*.d')
clean: ; rm -f $(CRUFT); rm -f *.elf *.hex *.bin *.dump *.map; rm -rf $(BUILD_DIR)/*
nuke: clean
-rm -f *.hex *.bin *.dump *.map
The issue is in line:
$Q $(LD) -Xlinker -Map $(#:.elf=.map) $(LDFLAGS) -T $(LINKER_SCRIPT) $(BUILD_DIR)/$^ -o $#
For which the output is:
arm-none-eabi-gcc -Xlinker -Map demo.map -nostartfiles -specs=nosys.specs -T LPC17xx.ld build/objs/modbus/ascii/mbascii.o modbus/functions/mbfunccoils.o modbus/functions/mbfuncdiag.o modbus/functions/mbfuncdisc.o modbus/functions/mbfuncholding.o modbus/functions/mbfuncinput.o modbus/functions/mbfuncother.o modbus/functions/mbutils.o modbus/port/port.o modbus/port/portevent.o modbus/port/portserial.o modbus/port/porttimer.o modbus/rtu/mbcrc.o modbus/rtu/mbrtu.o modbus/mb.o demo.o startup_LPC17xx.o system_LPC17xx.o -o demo.elf
The output command picks only the first object file from correct directory under build/objs.
Rest object file path doesn't have build/objs/.
Please anyone help me resolve this issue?
You are violating Mad Scientist's second rule of makefiles, and inviting more problems than you know.
Look at these rules (simplified):
$(TARGET).elf: $(OBJS)
$(LD) $(BUILD_DIR)/$^ -o $#
$(OBJS): %.o: %.c
$(CC) -c $< -o $(BUILD_DIR)/$#
Suppose the build directory is build/ and the object file is build/foo.o. The target of the second rule is foo.o, but what it actually builds is build/foo.o. Likewise, the first rule claims foo.o as a prerequisite, but it doesn't actually use foo.o, it uses build/foo.o These two errors cancel each other out, in a sense; Make succeeds in building the main target. But as you have found, it has trouble if there is more than one object file, because if the prerequisite list is foo.o bar.o, then
`$(BUILD_DIR)/$^`
expands to
build/foo.o bar.o
Also, Make will run the second rule even if build/foo.o exists and is up to date, and will fail to run it if foo.o exists. The target of a non-PHONY rule should be the name of the file it builds, and a non-PHONY prerequisite should be the name of a file whose existence is relevant:
$(TARGET).elf: $(BUILD_OBJS)
$(LD) $^ -o $#
$(BUILD_OBJS): $(BUILD_DIR)/%.o: %.c
$(CC) -c $< -o $#

Makefile recompiles everything

I know this question have been up multiple times but I can't seem to find my problem anyway.
The object and dependency files are created in their own folders. But it seems that they are not used when recompiling. What have I done wrong?
I have followed http://make.mad-scientist.net/papers/advanced-auto-dependency-generation/#combine for the generation of dependency files.
APP = test
OBJDIR = obj
DEPDIR = dep
HDRS = -Ibuild/src_generated -Isrc -Isrc/client -Isrc/server -Ideps -Iinclude -Iplugins
SRCS = $(wildcard build/src_generated/*.c) \
$(wildcard src/*.c) \
$(wildcard src/client/*.c) \
$(wildcard src/server/*.c) \
$(wildcard deps/*.c) \
plugins/ua_accesscontrol_default.c \
plugins/ua_clock.c \
plugins/ua_config_default.c \
plugins/ua_debug_dump_pkgs.c \
plugins/ua_log_stdout.c \
plugins/ua_network_tcp.c \
plugins/ua_nodestore_default.c \
plugins/ua_pki_certificate.c \
plugins/ua_securitypolicy_none.c \
tutorial_server_datasource.c
SRCDIRS = ./build/src_generated ./src ./src/client ./src/server ./deps ./plugins
OBJS = $(patsubst %.c,$(OBJDIR)/%.o,$(SRCS))
POSTCOMPILE = #mv -f $(DEPDIR)/$*.Td $(DEPDIR)/$*.d && touch $#
CFLAGS = -Os -std=c99 -DUA_NO_AMALGAMATION
DEPFLAGS = -MT $# -MMD -MP -MF $(DEPDIR)/$*.Td
$(APP): buildrepo $(OBJS)
$(CC) $(OBJS) -o $# $(CFLAGS) $(HDRS) -s
$(OBJDIR)/%.o: %.c $(DEPDIR)/%.d
$(CC) $(DEPFLAGS) $(CFLAGS) $(HDRS) -o $# -c $<
$(POSTCOMPILE)
$(DEPDIR)/%.d: ;
.PRECIOUS: $(DEPDIR)/%.d
include $(wildcard $(patsubst %,$(DEPDIR)/%.d,$(basename $(SRCS))))
.PHONY: clean
clean:
rm -rf $(OBJDIR)/*
rm -rf $(DEPDIR)/*
rm -rf $(APP)
buildrepo:
#$(call make-repo)
define make-repo
for dir in $(SRCDIRS); \
do \
mkdir -p $(OBJDIR)/$$dir; \
mkdir -p $(DEPDIR)/$$dir; \
done
endef
This line:
include $(wildcard $(patsubst %,$(DEPDIR)/%.d,$(basename $(SRCS))))
Expects that all dependency files are in one folder. You probably want:
-include ${SRCS:%.c=$(OBJDIR)/%.d} # Note the leading -

How to make object file into a directory

Hi using the below make file how can I create all the object files in to a directory obj.
May be this question is very simple but no idea how to do it ?
Makefile
# Makefile
#### variables
RM= rm -vf
CXX = g++
CXXFLAGS = -Wall -g
CPPFLAGS = -I/usr/include/opencv -I/usr/include/opencv2
LDLIBS = -pthread -lbluetooth -lopencv_core -lopencv_imgproc -lopencv_highgui \
-lopencv_ml -lopencv_video -lopencv_features2d \
-lopencv_calib3d -lopencv_objdetect -lopencv_contrib \
-lopencv_legacy -lv4l1 -lv4l2 -lv4lconvert
SOURCEFILES = main.cpp \
bluetooth.cpp \
gpio.cpp \
wifi.cpp \
capturAndSend.cpp \
OBJECTFILES = $(patsubst %.cpp,%.o,$(SOURCEFILES))
PROGNAME= server
### rules
.PHONY: all clean
all: $(PROGNAME)
$(PROGNAME): $(OBJECTFILES)
$(LINK.cpp) $^ $(LOADLIBES) $(LDLIBS) -o $#
clean:
$(RM) $(OBJECTFILES) $(PROGNAME)
There are lots and lots of answers to this question available already. Did you look?
Try:
OBJECTFILES = $(patsubst %.cpp,obj/%.o,$(SOURCEFILES))
...
obj/%.o : %.cpp
$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c -o $# $<

addprefix command not recognized in makefile using nmake.exe windows

all: prd.exe
CC=cl
CFLAGS=-O2 -I../src -I. /W4
LDFLAGS = /Zi
LIBSRC = $(addprefix ../lib/, \
open.c malloc.c \
) \
$(addprefix ../src/, \
main.c \
) \
helper.c
LIBOBJS = $(LIBSRC:.c=.o)
prd.exe: ../src/main.obj
$(CC) $(LDFLAGS) -Fe$# *.o
../src/main.obj: ../src/main.c
$(CC) $(CFLAGS) $(LIBOBJS) -c $< -Fo $#
.c.o:
$(CC) $(CFLAGS) $(LIBOBJS) -c $< -Fo $#
.c.i:
$(CC) $(CFLAGS) $(LIBOBJS) -C -E $< > $#
clean:
del /s /f /q ..\lib\*.o ..\src\*.o *.o *.exe *.pdb
distclean: clean
I get this error
fatal error U1000: syntax error : ')' missing in macro invocation at line 6
Am i missing something here? nmake does recognize addprefix, right?
No, addprefix is a GNU make extension. You have a GNUmakefile that requires GNU make (gmake) to process.
Alternatively, you could rewrite the GNU makefile to not use GNU extensions. In your case this should be easy:
LIBSRC = $(addprefix ../lib/, \
open.c malloc.c \
) \
$(addprefix ../src/, \
main.c \
) \
helper.c
becomes
LIBSRC = ../lib/open.c ../lib/malloc.c ../src/main.c helper.c

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