Recently I've been working on a open-source DLA named dnnweaver. But I got some errors when I tried to create a vivado project through the way on its github resposity.
1, the instruction file says "We will also use the DDR1 IP to create a clock for DnnWeaver. To do this, specify 150MHz as the frequency for c0_ddr4_ui_clk by double-clicking the IP and then specifying 150 MHz in the Advanced Clocking tab." But I found that c0_ddr4_ui_clk couldn't be modified.
2, because of the c0_ddr4_ui_clk, I tried to use another clock for dnnweaver module. But I've been getting timing errors.
really need some help...
Related
I am trying to simulate the lwIP example simulation on OMNET 5.6.1. I am using INET 4.2.4. The simulation I am trying to run can be found at inet/examples/inet/nclients/omnetpp.ini When I try to run it, it gives me the following error:
"Class "inet::TcpLwip" not found -- perhaps its code was not linked in, or the class wasn't registered with Register_Class(), or in the case of modules and channels, with Define_Module()/Define_Channel()--in module (omnetpp::cModules) NClients (id=1), during network setup."
I am new to OMNET++ and will appreciate your guidance on what to do.
By default the LWiP feature is not turned on in INET. You should either open the INET project's properties dialog in the IDE and on the OMNeT++ page find the Project Fetures list and enable TcpLwip, or from the command line (standing in the INET directory) execute opp_featuretool enable TcpLwip and then call make makefiles and then rebuild.
How can I modify the cache architecture in the gem5 simulator? I want to be able to configure the cache so that it is used differently (either set-associative or fully associative) depending on a certain execution mode?
I am new to gem5 and still finding my way. Where can I change the modelling of the cache architecture and how it is used in the source files?
Thanks!
You can change the modelling of the cache architecture by changing the Tags. The Tags are instantiated in src/mem/cache/cache.py.
This modification can be done either by:
Creating a config file. It is the correct approach and will give you more control over the simulation (check Jason's tutorial http://learning.gem5.org/book/part1/simple_config.html to learn how to create a config file).
Quick and dirty approach by modifying the default value of Tags between BaseSetAssoc and FullyAssoc within the cache.py file. This, however, will not work towards your final goal of changing the model according to the execution mode.
I recently posted something with relation to this assignment but I have hit another stumbling block and can't seem to find the solution. I have got a 4 bit alu simulating but I am required to use a pre-written test bench provided to me by the teacher. I have imported the test bench file and un selected the check mark next to synthesis in the source file properties as instructed.
My unit under test as detected by the testbench source file is the entity .vhd file of my project and so all should be fine except that when I simulate the program it just simulates as per normal with no output in the tcl console regarding any of the assertions of which the testbench is composed.
I have obviously googled and got more instructions about how to do this but I couldn't get specific instructions for the vivado software. It talked about xilinx and there being a process window, which is nowhere to be seen in Vivado. I can't understand why this so seemingly simple thing is taking me so long to figure out. There aren't any syntax errors and it says in the messages near the compiler window that the testbench is being parsed. Here is a screenshot of my file structure in the vivado IDE.
Can anyone please tell me how to do this?
Thanks,
Simon.
When you simulate, it will use whatever is set as the top level simulation entity as the top level for that simulation. In your image, the test bench is selected in the project hierarchy, but the UUT is set as the top module. You need to right click your test bench, and choose 'Set as Top'.
I'm about to create a new wave from file in a VHDL project in Quartus, but I've failed to find waveform type in verification part of the place.
Where we add a new file to a project, what can I do?
I'm using the web edition of Quartus.
If you speak about Quartus 2 vector waveform, this tool is no longer supported since v.10.
I am trying to use fixed point numbers in my VHDL project, but I keep having trouble implementing the library (found here http://www.eda-stds.org/fphdl/fixed_pkg_c.vhdl). The error I receive when trying to simulate is this
<ufixed> is not declared
My question is how exactly should a library be implemented so it can be used? As of now I have added it to the project in the IEEE_PROPOSED library, but it is not working. All source code can be found here https://github.com/srohrer32/beamformer/tree/fixed_num, under the hdl folder and libraries folder.
Are you using modelsim? Are you using a project? If not... I find the best way is to first compile the library on its own. Open your modelsim.ini file and make a path to the library. Like this:
lib_test = c:/test/source/lib_test
Finally, compile your own code and make sure you use the -modelsimini switch on vcom modelsim command.
If you are using a project (which I don't like, they are not as flexible) then you can point the project to the library.
More help about modelsim compiling with commands:
http://www.tkt.cs.tut.fi/tools/public/tutorials/mentor/modelsim/getting_started/gsms.html#compiling
Not being an isim user myself, a search through the ISim User Guide implies you need to create a separate project to compile into a library, contrasting with how easy it is to target a library from the command line.
Presumably you'd also need to add the library as a resource in your project. Funny there are no complaints about that yet you have:
library ieee_proposed;
in delay_calculation.vhd, noting that a library declaration simply makes the name available. Somewhere the implementation dependent mapping for the library name to library needs to be made. This by default is in xilinxisim.ini, but I imagine your project management interface allows you to map the library into your project, and isim should know where to look for the library.
Nosing around the user guide may be worthwhile.
In Simulation Steps Overview
User Libraries
Depending upon how you launch ISim, there are different methods
available to add user libraries:
When launching Project Navigator, define the user libraries in the ISE tool. See “Working with VHDL Libraries” in ISE Help for
details.
When using ISim standalone, interactive command mode, or non-interactive mode, set the library mapping file (see Appendix A,
Library Mapping File (xilinxisim.ini) to point to your logical or
physical libraries.
When launching ISim from the PlanAhead tool, define the user libraries in that tool. See the PlanAhead User Guide (UG632) for more
information. Appendix D, Additional Resources, contains a link to the
document.
See Working with VHDL Libraries, see To Create a VHDL Library and To Add Files to a VHDL Library.
(The top level link to ISE Help).
You'd think there'd be a FAQ for those of us apostate - speed reading 'religious' tomes sucks even using Google to find them. Notice the explanations are in terms of menu pull down actions, analogous to command line entry. We're being bitten by what's available on the top menu bar. And when you do manage to add and use a library successfully you'll remember how until someone changes the menus around, and you could of course wonder about documentation lagging.
Presumably what you've tried to do is set up the library mapping for synthesis mode in the ISE GUI, which is straightforward but completely ignored by iSim since it has its own system for managing library mappings. I'm not an iSim user but after looking at the documentation and a little testing it looks like the easiest way to set up a library is from the command line:
# This creates an ieee_proposed directory with a partially compiled object.
vhpcomp --work ieee_proposed=ieee_proposed fixed_pkg_c.vhdl
# Add a mapping from the logical library to the physical path.
# *nix shown. Windows would be similar or just use a text editor.
# <logical name>=<physical path>
echo ieee_proposed=`pwd`/ieee_proposed >> path/to/your/xilinxisim.ini
Make sure the xilinxisim.ini file is visible to iSim and it should pick up the mapping to your compiled library. You should be able to keep running vhpcomp from the parent of ieee_proposed to add more files to the library. You may have to manually copy the system default version to maintain the standard library mappings.