I have a block design with a Zynq and Microblaze on an Xilinx Zed board.
I want the microblaze to be able to access DDR memory shared with the arm corers in the PS. My microblaze uses a cache. There are two AXI ports on the microblaze M_AXI_DC, M_AXI_IC that need to be connected so that they have access to the PS DDR memory.
The microblaze ports are AXI4, Zynq uses AXI3. How to connect M_AXI_DC, M_AXI_IC?
2.1. A shared smart interconnect for both IC and DC ports?
mb M_AXI_DC, M_AXI_IC <-smart interconnect-> S_AXI_HP0
or
2.2. Two separate smart interconnects for the ports?
mb M_AXI_DC <-smart interconnect 1-> S_AXI_HP0 zynq
mb M_AXI_IC <-smart interconnect 2-> S_AXI_HP1 zynq
or maybe
2.3. One smart interconnect connected to HP0 and HP1:
mb M_AXI_DC S_AXI_HP0 zynq
<-smart interconnect 1->
mb M_AXI_IC S_AXI_HP1 zynq
2.3. Does approach 2.1, 2.2 or 2.3 differ in performance?
Approach 2.3 is most efficient use of PL resources for cache access. Think of the interconnect as a router. You need one for the Cache ports and a separate one for the peripherals.
What you seem to have left off is the DP port. That port is how data moves from DDR to the mb. If you move a lot data, then you have use a DMA instead.
See xapp1093 Page 3 Figure 1. has a diagram showing a complete design with code.
Related
I have nexys 4 ddr board which has 128MiB on board memory and I access it via IP inside Vivado named Memory Interface Generator. But for example unlike BRAM IP which has a .coe file that initialize BRAMs of the board, here for ddr memory of the board I cannot find a way to initialize it with some data. I have a Ibex processor that utilize this memory as its main memory but now I don't know how to put compiled codes that I have written inside this ddr2 memory. Can anyone help? Is there a way to boot these memories with some initial data easily like BRAMs?
For using an external memory like DDR2 as your processor main memory, you have to use a boot loader. Boot loader programs are small and can be run on the BRAM inside the FPGA. When the board is powered up, it reads the main program from external non-volatile memory (like SPI Flash) and loads it on the external DDR2.
I am not familiar with the processor you are using, but Xilinx has a template SREC-Bootloader in Vitis for its Microblaze processors. You can use that as start point and write your own bootloader.
I'm using zynq7000 family fpga, i want to write data from my fpga to micron ddr3 sdram memory without using PS logic (only using PL) I'm new to memory based designs may i get any help to design the logic using PL or any references.
Thanks in advance.
The biggest question is this: how is your "micron ddr3 sdram" physically connected to the FPGA? Is it pinned out for the PS-side? Or the PL? There are dedicated pins on the FPGA just for PS side memory. Now, if you absolutely must have PL logic interface with PS memory, then you can open an AXI port on the Zynq PS side to allow PL logic to get at the PS memory space. That's the only way to do it.
On the other hand, if the DDR is correctly pinned out to PL, then you can use the Xilinx Memory Interface Generator (MIG) IP core to build the PL-side logic to interface with it. See here.
I'm actually studying into the MicroBlaze micro controller system that I've implemented in my FPGA. But I want to understand how is working this MCU. Let's consider this block diagram :
MicroBlaze MCS block diagram
We can see that the processor is connect though 2 bus of 32 bits into a BRAM module. One of these bus is the ILMB (Instruction Local Memory Bus) and the other is DLMB (Data Local Memory Bus). We can see that both are connect to different port of the BRAM Module. So there is my question : In an Harvard Architecture, the program instructions and the random access memory is not supposed to be separated ? When we generate the system with the Xilinx IP Core Generator, the memory size that we put in is the size for the program instructions, the RAM or both ?
Memory size?
I've searched into the define in the xparameters.h header file to find the adress in memory of the ILMB and the DLMB and I've found that both are the same adress range.
#define XPAR_DLMB_CNTLR_BASEADDR 0x00000000
#define XPAR_DLMB_CNTLR_HIGHADDR 0x00003FFF
#define XPAR_ILMB_CNTLR_BASEADDR 0x00000000
#define XPAR_ILMB_CNTLR_HIGHADDR 0x00003FFF
The fact that both Instruction and Data are referred at the same adress confused me. Can someone tell me where I'm wrong ?
Both ILMB and DLMB buses in this case are sharing the same physical memory space. The same applies to the memory size parameter. By default Mircoblaze system is configured to have shared data and instruction memory space.
But the fact there are 2 separate busses allows you to configure your system to have data and instructions residing in totally different address spaces (or physical devices). For example, ILMB can be configured to address on a ROM memory and data can access completely different hardware block of RAM memory.
Microblaze is highly configurable CPU, and separate memory busses is one of these configuration points that needs to be configured in very rare cases. Most of the time these share the same address space of the BRAM memory.
I'm building something on a zybo board, so using a Zynq device.
I'd like to write into main memory from the CPU, and read from it with the FPGA in order to write the CPU results out to another device.
I'm pretty sure that I need to use the AXI bus to do this, but I can't work out the best approach to the problem. Do I:
Make a full AXI peripheral myself? Presumably a master which issues read requests to main memory, and then has them fulfilled. I'm finding it quite hard to find resources on how to actually make an AXI peripheral, where would I start looking for straightforward explanations.
Use one of the Xilinx IP cores to handle the AXI bus for me, but there are quite a few of them, and I'm not sure of the best one to use.
Whatever it is, it needs to be fast, and it needs to be able to do large reads from the DDR memory on my board. That memory needs to also be writable by the CPU.
Thanks!
An easy option is to use the AXI-Stream FIFO component in your block diagram. Then you can code up an AXI-Stream slave to receive the data. So the ARM would write via AXI to the FIFO, and your component would stream data out of the FIFO. No need to do any AXI work.
Take a look at Xilinx's PG080 for details.
If you have access to the vivado-hls tool.
Then transferring data from the main memory to the FPGA memory (e.g., BRAM) under a burst scheme would be one solution.
Just you need to use memcpy in your code and then the synthesis tool automatically generates the master IP which is very fast and reliable.
Option 1: Create your own AXI master. You would probably need to create a AXI slave for configuration purposes as well.
I found this article quite helpful to get started with AXI:
http://silica.com/wps/wcm/connect/88aa13e1-4ba4-4ed9-8247-65ad45c59129/SILICA_Xilinx_Designing_a_custom_axi_slave_rev1.pdf?MOD=AJPERES&CVID=kW6xDPd
And of course, the full AXI reference specification is here:
http://www.gstitt.ece.ufl.edu/courses/fall15/eel4720_5721/labs/refs/AXI4_specification.pdf
Option 2: Use the Xilinx AXI DMA component to setup DMA transfers between DDR memory and AXI streams. You would need to interface your logic to the "AXI streams" of the Xilinx DMA component. AXI streams are typically easier to implement than creating a new high performance AXI master.
This approach supports very high bandwidths, and can do both continous streams and packet based transfers. It also supports metadata for each packet.
The Xilinx AXI DMA component is here:
http://www.xilinx.com/products/intellectual-property/axi_dma.html
Xilinx also provides software drivers for this.
DMA controllers are present on disks, networking devices. So they can transfer data to main memory directly. Then what is use of the dma controller inside processor chip ?Also i would like to know, if there are different buses (i2c, pci, spi) outside of processor chip and only one bus (AXI) inside processor. how does this work?(shouldn’t it result in some bottleneck)
The on-chip DMA can take the task of copying data from devices to memory and viceversa for simple devices that cannot implement a DMA of their own. I can think that such devices can be a mouse, a keyboard, a soundcard, a bluetooth device, etc. These devices have simple logic and their requests are multiplexed and sent to a single general purpose DMA on the chip.
Peripherals with high bandwidths like GPU cards, Network Adapters, Hard Disks implement their own DMA that communicates with the chip's bus in order to initiate uploads and downloads to the system's memory.
if there are different buses (i2c, pci, spi) outside of processor chip
and only one bus (AXI) inside processor. how does this work?(shouldn’t
it result in some bottleneck)
That's actually simple. The on-chip internal AXI bus is much faster - running at a much higher frequency (equal or in the same range to the CPU's frequency) (has a much higher bandwidth) than all the aggregated bandwidths of i2c+pci+spi. Of course multiple hardware elements compete on the AXI bus but usually you have priorities implemented and different optimization techniques.
From Wikipedia:
Direct memory access (DMA) is a feature of computerized systems that allows certain hardware subsystems to access main system memory independently of the central processing unit (CPU). [...] A DMA controller can generate memory addresses and initiate memory read or write cycles. It contains several processor registers that can be written and read by the CPU. These include a memory address register, a byte count register, and one or more control registers.