My Makefile contains a clean rule, but for some reason it always fails, even though running the command by itself is always successful. What could possibly be causing this?
make clean
del /f *.o *.hex *.elf *.map
make: *** [clean] Error 1
Edit: Here is the whole makefile:
MCU = atmega324p
AVRDUDE_DEVICE = m324p -F
PORT = \\\\.\USBSER000
CFLAGS=-g -Wall -mcall-prologues -mmcu=$(MCU) -Os
CC=avr-gcc
OBJCOPY=avr-objcopy
OBJDUMP=avr-objdump
LDFLAGS=
TARGET=led_strip
all: $(TARGET).hex
%.hex: %.elf
$(OBJCOPY) -R .eeprom -O ihex $< $#
%.elf: %.o
$(CC) $(CFLAGS) $^ $(LDFLAGS) -o $#
program: $(TARGET).hex
bootloadHID.exe -r $<
clean:
del /f *.o *.hex *.elf *.map
In the meantime, I realised that WinAVR very rudely overwrote my PATH variable when I installed it. I went and added MinGW back to my PATH and removed the WinAVR utils/ folder which contained commands like sh.exe, and that seems to have fixed the issue. I would still like to understand what exactly was causing the problem, though.
Related
i want to use mingW32_make.exe to compile a C code on command prompt. The error message shows
rm -f obj/*.o
process_begin: CreateProcess(NULL, rm -f obj/*.o, ...) failed.
make (e=2): The system cannot find the file specified.
makefile:11: recipe for target 'all' failed
mingw32-make.exe: *** [all] Error 2
The makefile is show below
CC=gcc
INC_DIR=../include
LIBS=-lregex
ODIR=obj
_OBJ=main.o BVPA.o BVPA-cube.o BVPA-cif.o BVPA-hk.o BVPA-path.o BVPA-math.o BVPA-cmd.o BVPA-gui.o BVPA-vesta.o MT19937AR.o
OBJ=$(patsubst %,$(ODIR)/%,$(_OBJ))
TARGET=../bin/BVPA_win.exe
CFLAGS=-I$(INC_DIR) -Wall -g
all: $(TARGET)
rm -f $(ODIR)/*.o
$(TARGET): $(OBJ)
$(CC) $(CFLAGS) -o $# $^ $(LIBS)
$(ODIR)/%.o: %.c
$(CC) $(CFLAGS) -c -o $# $^
clean:
rm -f $(ODIR)/*.o
'''
I have encountered the same question and here is the fix. The reason is given from other's comments:
Windows does not understand rm.
When you run make clean, it will clear out all .o files.
clean:
del *.o
The answer for this question is actually simple. There is no obj folder in your current directory so the compiler doesn't know where to add or remove. You can simply add a obj folder in your source code directory.
I come across the same issue, and my solution is below
del /f $(ODIR)\*.o
Note that if I use "$(ODIR)/*.o" in the makefile, the error would still exist.
My project's directory is mounted via NFS. From the directory under which it is mounted, I call make -f msh/Makefile cd=msh. (msh is my mount.) cd is a variable in the Makefile that is prepended to source files. This works fine with source files directly under cd. However, if the source files are under a subdirectory within cd, Make fails, saying that there is no rule to make that target. It does not fail if I call Make from within my mount.
This is my Makefile.
CC?=gcc
CFLAGS:=-Wall -Werror -D_POSIX_C_SOURCE=200112L $(CFLAGS)
cd?=.
objects_nix=if/tty.o
objects:=sub.o if.o $(objects_nix)
ifdef SO
CFLAGS+=-fPIC
bin=libmsh.so
else
bin=libmsh.a
endif
.PHONY : clean
$(bin) :
libmsh.a : $(objects)
$(AR) -r -c -s $# $(objects)
libmsh.so : $(objects)
#echo
#echo If you have resumed compilation after not having used the SO flag,
#echo you should run make clean.
#echo
$(LD) $(LDFLAGS) -shared -o $# $(objects)
test : $(cd)/test.c $(bin)
ifdef SO
$(CC) $(CFLAGS) -I$(cd) $(LDFLAGS) -L. -lmsh -Wl,-rpath,. -o $# $(cd)/test.c
else
$(CC) $(CFLAGS) -I$(cd) $(LDFLAGS) -o $# $(cd)/test.c $(bin)
endif
%.o : $(cd)/%.c
$(CC) $(CFLAGS) -c -o $# $<
clean :
rm -f libmsh.so libmsh.a
rm -f $(objects)
rm -f test.o test
I have tried creating another rule for the subdirectory, and this works. But I'd like it to work with only the one rule.
You have told Make how to make a .o file from .c file in $(cd). It does not know how to make a .o file if the .c file in some other directory. You can solve this in various ways, such as:
Add an explicit rule for all directories. You have already done that.
Use VPATH.
Create a Makefile for each directory.
I took a makefile from a previous project that compiles programs for an avr microcontroller. I ran into some problems with what IO ports/data directional addresses I was setting which was causing the microcontroller to fault and reset. Because of this I wanted to add a step in my makefile to have it generate the pre-proccessed files and then compile from these preprocessed files. I'm not too familiar with how rules/dependencies work in makefiles so I've made, what I believe is, a simple mistake in my understanding of how makefiles work. My rules to make the preprocessed files/object files and eventually the .elf file must be wrong. Up until I added the steps which attempted to create the preprocessed files creating the .elf file work fine. What is my simple mistake/understanding in how rules/dependencies work in make?
How I view this working is when I ask to make all it sees that it has a dependency of led.elf. To create this it has the dependency of the preprocessed files based on the line of $(OUTPUT).elf: $(PROCESS_FILES) so it starts with this line. When I try to make all however I get the error make: *** No rule to make target 'main.c', needed by 'main.e'. Stop. and I don't understand why. Can anyone help my understanding in make files?
SRC_FILES=\
main.c led.c comm.c
#Object files
PROCESS_FILES=$(SRC_FILES:.c=.e)
OBJ_FILES=$(PROCESS_FILES:.e=.o)
#Directories where to look for include files
INC_DIRS=\
-I. \
#Output file name
OUTPUT=led
#Programmer and port
PROG=dragon_isp
PORT=usb
#Debugging host and port
DHOST=localhost
DPORT=6423
#Compiler related params
MCU=atmega2560
CC=avr-gcc
OBJCOPY=avr-objcopy
CFLAGS= -mcall-prologues -std=gnu99 -funsigned-char -funsigned bitfields \
-fpack-struct -fshort-enums -mmcu=$(MCU) -Wall -Wstrict-prototypes \
$(INC_DIRS)
#Optimization level
CFLAGS+=-Os
#Debug info
CFLAGS+=-gdwarf-2
#Generate hex file ready to upload
all: $(OUTPUT).elf
$(OBJCOPY) -R .eeprom -O ihex $(OUTPUT).elf $(OUTPUT).hex
#Link output files
$(OUTPUT).elf: $(PROCESS_FILES)
$(CC) $(CFLAGS) $(OBJ_FILES) -o $(OUTPUT).elf -Wl,-Map,$(OUTPUT).map
#Create object files
$(PROCESS_FILES): %.e : %.c
$(CC) -E $(CFLAGS) $< -o $#
$(OBJ_FILES): %.o : %.e
$(CC) -x $(CFLAGS) $< -o $#
#Create assembler file of a C source
%.s: %.c
$(CC) -S $(CFLAGS) $< -o $#
#Cleans all generated files
clean:
rm -f $(OBJ_FILES)
rm -f $(OUTPUT).elf
rm -f $(OUTPUT).hex
rm -f $(OUTPUT).map
Edit: I'm away from my computer now so I can't check this but thinking about my issue I'm starting to think I don't have a file named main.c in that directory. Even if I did I still think the makefile would not work correctly because I don't fully understand rules in makefiles.
My error was coming from the fact that I did not have a main.c file in my directory. Make sure you backup files when you're messing with the OBJ_FILES or similar variable and have a line that will delete whatever is in that variable upon a make clean.
As for the rules, I had to make one small fix to achieve what I wanted. I changed
$(OUTPUT).elf: $(PROCESS_FILES)
$(CC) $(CFLAGS) $(OBJ_FILES) -o $(OUTPUT).elf -Wl,-Map,$(OUTPUT).map
to
$(OUTPUT).elf: $(OBJ_FILES)
$(CC) $(CFLAGS) $(OBJ_FILES) -o $(OUTPUT).elf -Wl,-Map,$(OUTPUT).map
This then sees it needs the object files which in turn needs the preprocessed files.
Edit: I also changed OBJ_FILES=$(PROCESS_FILES:.e=.o) to OBJ_FILES=$(SRC_FILES:.c=.o). I also added $(PROCESS_FILES) to $(OUTPUT).elf: $(OBJ_FILES) so the rule would generate both the preprocessed files and object files independently. I had to change $(OBJ_FILES): %.o : %.e to $(OBJ_FILES): %.o : %.c to make this work.
I'm writing a piece of software that utilizes a Makefile for compilation, originally I had a rule setup for each file however this proved to be too cumbersome whenever I added a new file. To try and automate the process I did some research and learnt that GCC/G++ can automatically build Makefile rules with the -M flag.
There are many examples of this being done with a simple directory structure however my ideal directory structure looks like this:
src/
kernel.hpp kernel.cpp
Types/
String.cpp
String.hpp
Drivers/IO-Ports/
CMOS.cpp
CMOS.hpp
...
build/
DEPS/
kernel.d
Types/String.d
...
OBJ/
kernel.o
Types/String.o
...
My current Makefile:
CCHOME=/home/dan/opt/cross/bin
CC=#$(CCHOME)/i586-elf-g++
CFLAGS=-ffreestanding -O2 -Wextra -Wall -fno-exceptions -fno-rtti
KernelName=CPlusKern
QEMU=qemu-system-x86_64 -monitor stdio
SrcDIR=src
SourceDIRS:=$(shell find $(SrcDIR) -type d)
SrcFILES=$(shell find $(SrcDIR) -type f -name *.cpp)
HdrFILES=$(shell find $(SrcDIR) -type f -name *.hpp)
DepDIR=$(BuildDIR)/DEPS
DepFILES0=$(subst $(SrcDIR), $(DepDIR),$(SrcFILES))
DepFILES=$(subst .cpp,.d,$(DepFILES0))
ObjDIR=$(BuildDIR)/OBJ
ObjDIRS=$(subst $(SrcDIR),$(ObjDIR),$(SourceDIRS))
ObjFILES0=$(subst $(SrcDIR), $(ObjDIR),$(SrcFILES))
ObjFILES=$(subst .cpp,.o,$(ObjFILES0))
BuildDIR=build
BuildDIRS=$(BuildDIR) $(ObjDIR) $(DepDIR)
all: assemble compile run
image: assemble compile build-image run-image
debug:
#echo "BuildDIRS: " $(BuildDIRS)
#echo "DepFiles: " $(DepFILES)
#echo "SrcFiles: " $(SrcFILES)
#echo "ObjFiles: " $(ObjFILES)
./src/kernel.o: ./src/kernel.cpp
#echo $(CC) $(CFLAGS) -MMD -MP -MF $< -o $(subst $(SrcDIR), $(ObjDIR),$#)
./src/kernel.cpp:
dir:
#echo "Making Build Dirs..."
#-mkdir -p $(BuildDIRS)
compile: dir $(ObjFILES)
# #echo "Compiling Source Files: " $(SrcFILES)
assemble: dir boot.o
#echo "Assembling Core Files..."
boot.o: $(SrcDIR)/boot.s
#$(CCHOME)/i586-elf-as $(SrcDIR)/boot.s -o $(ObjDIR)/boot.o
build: %.o
echo "Building Kernel Binary..."
#$(CC) -T linker.ld -o $(KernelName).bin -ffreestanding -O2 -nostdlib $(SrcFILES)-lgcc
build-image: build
#echo "Building Kernel Image..."
#cp $(KernelName).bin isodir/boot/$(KernelName).bin
#Scripts/MakeGrub.sh $(KernelName) isodir/boot/grub
grub-mkrescue -o $(KernelName).iso isodir
%.o: %.cpp Makefile
#echo "Building Object $#"
$(CC) $(CFLAGS) -MMD -MP -MF $(subst $(SrcDIR),$(DepDIR),$#) -o $(subst $(SrcDIR), $(ObjDIR),$#)
run:
#echo "Starting QEMU"
#$(QEMU) -kernel $(KernelName).bin
run-image:
#echo "Starting QEMU"
#$(QEMU) -bios OVMF.fd -cdrom $(KernelName).iso
clean:
#echo "Cleaning Build Directories..."
-#rm -R $(BuildDIR) ./isodir
-#$(RM) $(KernelName).bin $(KernelName).iso
I thought this might do the trick however make throws an error:
make: *** No rule to make target `build/OBJ/VGA.o', needed by `compile'. Stop.
I can't determine how to make the rule:
%.o: %.cpp Makefile
$(CC) $(CFLAGS) -MMD -MP -MF $(subst $(SrcDIR),$(DepDIR),$#) -o $(subst $(SrcDIR), $(ObjDIR),$#)
apply to every .cpp file. As far as I know wildcards cannot be used in rule definitions.
I'm not sure if this helps but the path/name of each source file is stored in the $(SrcFILES) variable.
Just to clarify, here is an expanded version of the above rule:
/home/dan/opt/cross/bin/i586-elf-g++ -ffreestanding -O2 -Wextra -Wall -fno-exceptions -fno-rtti -MMD -MP -MF src/kernel.cpp -o build/OBJ/kernel.o
And the generated dependency file for this instance:
kernel.o: src/kernel.cpp src/kernel.hpp src/Globals.hpp \
src/VGATerminal.hpp src/Types/String.hpp src/Types/../Globals.hpp \
src/VGA.hpp src/IO/Read.hpp src/IO/Write.hpp \
src/Drivers/IO-Ports/CMOS.hpp src/Drivers/IO-Ports/../../IO/Read.hpp \
src/Drivers/IO-Ports/../../IO/Write.hpp
This is my first post here so feedback on my question is appreciated :)
Hopefully I can get this out of the way and get back to developing my code.
EDIT:
The rule provided by #Beta worked without a problem, All of my Object files successfully build and are output in the right place. This rule even picked up build/OBJ/Drivers/IO-Ports/CMOS.o and build/OBJ/Drivers/PS2.o.
So now I can happily build all of the Objects individually if I pass the filename however I think I still need dependency resolution so that I don't have to write a rule for each file.
This may take a few iterations.
The first problem is that you have a target, build/OBJ/VGA.o and no corresponding rule. The rule
%.o: %.cpp Makefile
...
doesn't fit; it can build build/OBJ/VGA.o from build/OBJ/VGA.cpp, but there's no such source file.
So for a first step, if the source file is src/whatever/VGA.cpp, try this rule:
build/OBJ/%.o: src/whatever/%.cpp
...
and tell us the result.
EDIT:
Good, now try this:
build/OBJ/%.o: src/%.cpp
...
I downloaded this Makefile and I'm having a hard time understanding how it works.
I am programming in Ocaml and for some module, I implemented an interface (.mli). Strangely, even when I add the .mli file before the corresponding .ml file, the Makefile seems to skip it; so I'm getting the error
could not find the X.cmi for the module X.
Worse, I added some file without the required .mli and strangely again the Makefile automatically added them to the list of sources.
I'm saying strangely but perhaps its perfectly normal to Makefiles expert.
I'm not an expert when it comes to Makefile, can anyone help me understanding how this Makefile works?
The compilation works fine, when I replace the line
$(EXEC): $(OBJS)
$(CAMLC) $(CUSTOM) -o $(EXEC) $(LIBS) $(OBJS)
With
$(EXEC): $(SOURCES)
$(CAMLC) $(CUSTOM) -o $(EXEC) $(LIBS) $(SOURCES)
and add the required .mli
Try
# Makefile
PRG =
# Fichiers dans l'ordre
ML =
MLI =
CMO=${ML:.ml=.cmo}
CMX=${ML:.ml=.cmx}
CMI=${ML:.mli=.cmi}
OCAMLFLAGS = -I
OCAMLLD = -ccopt -L.
OCAMLOPT = ocamlopt.opt
OCAMLC = ocamlc.opt
OCAMLDEP = ocamldep
${PRG}: ${OCAMLOPT} ${OCAMLFLAGS} ${OCAMLLD} -o $# ${CMX}
make clean
.SUFFIXES: .ml .mli .cmo .cmx .cmi
.ml.cmx:
${OCAMLOPT} ${OCAMLFLAGS} ${OCAMLLD} -c $<
.ml.cmo:
${OCAMLC} -c $<
.mli.cmi:
${OCAMLC} -c $<
clean:
rm -f *~ *.o *.cm? *mli
fullclean: clean
rm -f .depend ${PRG}
depend: .depend
.depend: ${ML} ${MLI}
rm -f .depend
${OCAMLDEP} ${ML} ${MLI} > .depend
include .depend
You'll have to setup PRG, ML, MLI, FLAGS, LD. :)