Automatic dependency resolution using GNU Makefile - gcc

Question

I'm writing a piece of software that utilizes a Makefile for compilation, originally I had a rule setup for each file however this proved to be too cumbersome whenever I added a new file. To try and automate the process I did some research and learnt that GCC/G++ can automatically build Makefile rules with the -M flag.
There are many examples of this being done with a simple directory structure however my ideal directory structure looks like this:
src/
kernel.hpp kernel.cpp
Types/
String.cpp
String.hpp
Drivers/IO-Ports/
CMOS.cpp
CMOS.hpp
...
build/
DEPS/
kernel.d
Types/String.d
...
OBJ/
kernel.o
Types/String.o
...
My current Makefile:
CCHOME=/home/dan/opt/cross/bin
CC=#$(CCHOME)/i586-elf-g++
CFLAGS=-ffreestanding -O2 -Wextra -Wall -fno-exceptions -fno-rtti
KernelName=CPlusKern
QEMU=qemu-system-x86_64 -monitor stdio
SrcDIR=src
SourceDIRS:=$(shell find $(SrcDIR) -type d)
SrcFILES=$(shell find $(SrcDIR) -type f -name *.cpp)
HdrFILES=$(shell find $(SrcDIR) -type f -name *.hpp)
DepDIR=$(BuildDIR)/DEPS
DepFILES0=$(subst $(SrcDIR), $(DepDIR),$(SrcFILES))
DepFILES=$(subst .cpp,.d,$(DepFILES0))
ObjDIR=$(BuildDIR)/OBJ
ObjDIRS=$(subst $(SrcDIR),$(ObjDIR),$(SourceDIRS))
ObjFILES0=$(subst $(SrcDIR), $(ObjDIR),$(SrcFILES))
ObjFILES=$(subst .cpp,.o,$(ObjFILES0))
BuildDIR=build
BuildDIRS=$(BuildDIR) $(ObjDIR) $(DepDIR)
all: assemble compile run
image: assemble compile build-image run-image
debug:
#echo "BuildDIRS: " $(BuildDIRS)
#echo "DepFiles: " $(DepFILES)
#echo "SrcFiles: " $(SrcFILES)
#echo "ObjFiles: " $(ObjFILES)
./src/kernel.o: ./src/kernel.cpp
#echo $(CC) $(CFLAGS) -MMD -MP -MF $< -o $(subst $(SrcDIR), $(ObjDIR),$#)
./src/kernel.cpp:
dir:
#echo "Making Build Dirs..."
#-mkdir -p $(BuildDIRS)
compile: dir $(ObjFILES)
# #echo "Compiling Source Files: " $(SrcFILES)
assemble: dir boot.o
#echo "Assembling Core Files..."
boot.o: $(SrcDIR)/boot.s
#$(CCHOME)/i586-elf-as $(SrcDIR)/boot.s -o $(ObjDIR)/boot.o
build: %.o
echo "Building Kernel Binary..."
#$(CC) -T linker.ld -o $(KernelName).bin -ffreestanding -O2 -nostdlib $(SrcFILES)-lgcc
build-image: build
#echo "Building Kernel Image..."
#cp $(KernelName).bin isodir/boot/$(KernelName).bin
#Scripts/MakeGrub.sh $(KernelName) isodir/boot/grub
grub-mkrescue -o $(KernelName).iso isodir
%.o: %.cpp Makefile
#echo "Building Object $#"
$(CC) $(CFLAGS) -MMD -MP -MF $(subst $(SrcDIR),$(DepDIR),$#) -o $(subst $(SrcDIR), $(ObjDIR),$#)
run:
#echo "Starting QEMU"
#$(QEMU) -kernel $(KernelName).bin
run-image:
#echo "Starting QEMU"
#$(QEMU) -bios OVMF.fd -cdrom $(KernelName).iso
clean:
#echo "Cleaning Build Directories..."
-#rm -R $(BuildDIR) ./isodir
-#$(RM) $(KernelName).bin $(KernelName).iso
I thought this might do the trick however make throws an error:
make: *** No rule to make target `build/OBJ/VGA.o', needed by `compile'. Stop.
I can't determine how to make the rule:
%.o: %.cpp Makefile
$(CC) $(CFLAGS) -MMD -MP -MF $(subst $(SrcDIR),$(DepDIR),$#) -o $(subst $(SrcDIR), $(ObjDIR),$#)
apply to every .cpp file. As far as I know wildcards cannot be used in rule definitions.
I'm not sure if this helps but the path/name of each source file is stored in the $(SrcFILES) variable.
Just to clarify, here is an expanded version of the above rule:
/home/dan/opt/cross/bin/i586-elf-g++ -ffreestanding -O2 -Wextra -Wall -fno-exceptions -fno-rtti -MMD -MP -MF src/kernel.cpp -o build/OBJ/kernel.o
And the generated dependency file for this instance:
kernel.o: src/kernel.cpp src/kernel.hpp src/Globals.hpp \
src/VGATerminal.hpp src/Types/String.hpp src/Types/../Globals.hpp \
src/VGA.hpp src/IO/Read.hpp src/IO/Write.hpp \
src/Drivers/IO-Ports/CMOS.hpp src/Drivers/IO-Ports/../../IO/Read.hpp \
src/Drivers/IO-Ports/../../IO/Write.hpp
This is my first post here so feedback on my question is appreciated :)
Hopefully I can get this out of the way and get back to developing my code.
EDIT:
The rule provided by #Beta worked without a problem, All of my Object files successfully build and are output in the right place. This rule even picked up build/OBJ/Drivers/IO-Ports/CMOS.o and build/OBJ/Drivers/PS2.o.
So now I can happily build all of the Objects individually if I pass the filename however I think I still need dependency resolution so that I don't have to write a rule for each file.

Answer 1

This may take a few iterations.
The first problem is that you have a target, build/OBJ/VGA.o and no corresponding rule. The rule
%.o: %.cpp Makefile
...
doesn't fit; it can build build/OBJ/VGA.o from build/OBJ/VGA.cpp, but there's no such source file.
So for a first step, if the source file is src/whatever/VGA.cpp, try this rule:
build/OBJ/%.o: src/whatever/%.cpp
...
and tell us the result.
EDIT:
Good, now try this:
build/OBJ/%.o: src/%.cpp
...