in VHDL, how to check if file exists before opening it? - vhdl

Question

In Verilog, I can check if a file exists by opening the file and then checking if the file descriptor is zero, and if it is not to assume the file doesn't exist. For example, as follows:
module testbench;
function file_exists;
input [80*8:0] filename;
integer file;
integer error;
begin
file = $fopen(filename, "r");
if (!file) begin
$display("\nFile Open Failed with Error Code = %x", error);
file_exists = 0;
end
else begin
$fclose(file);
file_exists = 1;
end
end
endfunction
integer x;
initial begin
x = file_exists("sdfsdf.txt");
$display("x: %0b", x);
end
endmodule
How can I do the same thing in vhdl?

Answer 1

When you open a file, for example:
file_open(status, file_handle, “my_file.txt”, read_mode);
You get a status of type file_open_status. It can have a number of values: open_ok, status_error, name_error and mode_error. You'll get name_error if the file isn't found

Answer 2

use ieee.std_logic_1164.all;
use std.textio.all;
entity testebench is
end entity;
architecture sim of testbench is
impure function file_exists(
filename : in string
) return boolean is
variable open_status :FILE_OPEN_STATUS;
file infile :text;
begin
file_open(open_status, infile, filename, read_mode);
if open_status /= open_ok then
return false;
else
file_close(infile);
return true;
end if;
end function;
begin
process
f1 :boolean;
begin
f1 = file_exists("fgsfgsdfg.txt")
report "found: " & boolean'image(f1);
end process;
end architecture;