I try to write VHDL simulation result at txt file.
I can write some data.
But i like to stack these data by row order. That is, there is new line between saved data.
I exptected writeline function to move newline. But it isn`t.
TEXT_OUT : process (I_CLK,I_RST)
file file_RESULTS : text open write_mode is "output_result.txt";
variable v_OLINE : line;
begin
if (I_RST = '1') then
null;
elsif (rising_edge(I_CLK)) then
if (I_BRAM_ENA = '1') then
hwrite(v_OLINE, O_ADDRB, left, 5);
writeline(file_RESULTS, v_OLINE);
report "Save the output address!";
end if;
end if;
end process;
if O_ADDRB have sequentially 0000, 0001, 0002, as time gone.
Then output_result.txt have data like below
0000
0001
0002
If you need to print in new line then probably I can't help you unless you have to do it all in one go, without having to close the file and open again (in which case you can follow as mentioned in comments by user1155120.
But if it is only for debugging purposes, then use this code to print in console:
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_textio.all;
procedure writeproc(sig: in std_logic_vector; s : string) is
variable li : line;
variable str : string(1 to sig'length);
file f_in : text; -- open read_mode is "output";
file f_out : text; -- open write_mode is "output";
begin
file_open(f_out, "output", write_mode);
write(li, std_logic_vector(sig));
write(li, lf); writeline(f_out, li);
file_close(f_out);
file_open(f_in, "output", read_mode);
readline(f_in, li);
read(li, str);
file_close(f_in);
report "read " & s & str;
end procedure writeproc;
Related
I wrote a VHDL code that should loop through a file and close the file and stop after the file ends and closes the file but it just keeps looping indefinitely reading from the file
FILE f : TEXT;
constant filename : string :="input.txt";
VARIABLE L : LINE;
variable al : integer ;
variable opcode_str : string(5 downto 1);
variable comma : character;
begin
File_Open (f,FILENAME, read_mode);
while not endfile(f) loop
readline (f, l);
read(l, opcode_str);
read(l, comma);
read(l, Al);
op_code<= read_opcode(opcode_str);
w_tb <=std_logic_vector(to_unsigned(Al, w_tb'length));
wait for 10 ns;
end loop;
File_Close (f);
end process
Your process has no wait statement at the end of the process. All processes with no sensitivity list are infinite loops.
Simply add the statement
wait; -- waits forever
at the end of the process.
Edit: Okay I am able to re read the first line. Problem now is that it keeps repeat the first line only and doesn't move on to the next line. From all the loops I see, it suppose to look like it would work.
I am working on a program for simulation purposes which reads hex data byte by byte from a text file and outputs it in a 1 bit per clock cycle.
I would like to reuse the same line multiple times after reading it before moving on to another read line. For testing purposes of whether it could re read the same line I used
inline2 := new string'(inline.all);
and copied and paste the same code below and changing some of the read variables. Which worked I was able to read the same line twice, however I am planning to use a while loop to implement it for quite a number of readings and I have trouble doing so.
I was whether is it possible or did I make a mistake again.
Basically my goal is for text file first line containing AA BB CC, 2nd line containing DD EE FF.
Setting
signal Seqcount: integer = := 0
Using a (while Seqcount loop of <3) I would like the output to be
AA BB CC
AA BB CC
AA BB CC
DD EE FF
DD EE FF
DD EE FF
I tried adding
While (Seqcount <3) loop
inline := new string'(inline.all);
followed by my read codes. However, it only read the data once and stopped. Without looping again.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.std_logic_textio.all;
LIBRARY STD;
USE STD.textio.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
entity readtext is
port (
IN_SRX2_BPSKDAT1: OUT std_logic
);
end readtext;
ARCHITECTURE arch_name OF readtext IS
signal readdatainput : std_logic_vector (7 downto 0);
signal linenumber : integer:=0;
signal Bitreading : std_logic;
signal Bitcount : integer := 0;
signal SeqCount: integer := 1;
BEGIN
clock <= not (clock) after 0.5 ms;
reading:
process
file infile : text is in "A.txt"; --A.txt contains AA 00 AA on the first line followed by BB 11 BB on next line.
variable inline : line; --line number declaration
variable inline2 : line; --line number declaration --test
file file_RESULTS : text;
variable inputdata : std_logic_vector(7 downto 0);
variable inputdata2 : std_logic_vector(7 downto 0); --test
begin
wait until rising_edge(clock);
while not endfile(infile) loop
readline(infile, inline);
inline := new string'(inline.all); --I was hoping this refresh the inline
while (SeqCount < 5) loop
inline := new string'(inline.all); --to copy line data to a new line
while inline.all'length /= 0 loop
hread (inline, inputdata);
readdatainput <= inputdata;
for i in inputdata'range loop
Bitreading <= inputdata(i);
IN_SRX2_BPSKDAT1 <= inputdata(i);
wait until rising_edge(clock);
end loop;--end of byte
inline := new string' (inline2.all);
end loop;-- end of line
SeqCount <= SeqCount+1; --this loops the program to read it a few more times.
end loop; -- end of while loop condition go to next line.
Seqcount <= 1;
end loop; -- end of file, it is suppose to repeat here
file_close(infile);
end process reading;
endoffile <='1'; --set signal to tell end of file read file is reached.
END ARCHITECTURE arch_name;
It is able to read the first line of data and repeat for the number of times of loop however it doesnt go on to the next line.
I have a file source.txt, it looks like this:
00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
0065006500660067006700690069006A006B006C006E
00650065006600670067006700680069006A006C006D
00650065006600670067006600660068006A006B006D
006500650066006700670065006600670069006B006D
00650065006600670067006600670068006A006C006D
0065006500660067006700690069006A006B006C006E
*
After each line there is the hidden newline character '\n'.
The asterix '*' is my visible end-of-file character.
How do I write a testbench in VHDL that does the following:
read file
store one line in a vector
write that vector in a new target.txt
Using VHDL-2008, and showing the std_logic_vector underway, the code can be:
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity tb is
end entity;
architecture syn of tb is
begin
process is
variable line_v : line;
file read_file : text;
file write_file : text;
variable slv_v : std_logic_vector(44 * 4 - 1 downto 0);
begin
file_open(read_file, "source.txt", read_mode);
file_open(write_file, "target.txt", write_mode);
while not endfile(read_file) loop
readline(read_file, line_v);
hread(line_v, slv_v);
report "slv_v: " & to_hstring(slv_v);
hwrite(line_v, slv_v);
writeline(write_file, line_v);
end loop;
file_close(read_file);
file_close(write_file);
wait;
end process;
end architecture;
is it possible to write a module code for a test bench? I have a test bench code that reads a text file and shows it in the Isim but I want to put this data on a port and process it. how can I get it out of simulation environment? how can I write a module for that in VHDL? thank you
, the code is here:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use STD.textio.all; --Dont forget to include this library for file operations.
ENTITY read_file IS
END read_file;
ARCHITECTURE beha OF read_file IS
signal bin_value : std_logic_vector(2 downto 0):="000";
BEGIN
--Read process
process
file file_pointer : text;
variable line_content : string(1 to 3);
variable line_num : line;
variable j : integer := 0;
variable char : character:='0';
begin
--Open the file read.txt from the specified location for reading(READ_MODE).
file_open(file_pointer,"C:\read.txt",READ_MODE);
while not endfile(file_pointer) loop --till the end of file is reached continue.
readline (file_pointer,line_num); --Read the whole line from the file
--Read the contents of the line from the file into a variable.
READ (line_num,line_content);
--For each character in the line convert it to binary value.
--And then store it in a signal named 'bin_value'.
for j in 1 to 3 loop
char := line_content(j);
if(char = '0') then
bin_value(3-j) <= '0';
else
bin_value(3-j) <= '1';
end if;
end loop;
wait for 10 ns; --after reading each line wait for 10ns.
end loop;
file_close(file_pointer); --after reading all the lines close the file.
wait;
end process;
end beha;
Instead of just taking input from a file and writing output to a file, is there a way to dynamically creating a file from the VHDL design??
I am trying to create multiple files depending on number of fpgas connected to the system ( which can be varying).
thanks in advance
Not sure I understand your question, but maybe you mean this:
process
file outputf : text;
begin
file_open(outputf, "path/to/file", WRITE_MODE); -- READ_MODE and APPEND_MODE as the other options
-- Do your file operation as usual
file_close(outputf);
end process;
Create a file name based on the instance of some entity:
each file created has the postfix of 'DATA_NAME' (for example)
Is this what you mean?
entity ENTITY_NAME is
generic (
DATA_NAME : Character := '1'
);
port (
...
);
architecture rtl of ENTITY_NAME is
[signals]
file file_out : TEXT open write_mode is "data_out/ENTITY_NAME" & DATA_NAME & ".txt";
begin
Proc_Data_Output : process
variable line_out : LINE;
begin
d_inout <= "ZZZZZZZZZZZZZZZZ";
write (line_out, string'("Data: "));
hwrite (line_out, d_inout);
writeline (file_out, line_out);
end process;
end rtl;