I have this makefile:
src = $(notdir $(wildcard src/*.cpp))
obj = $(src:.cpp=.o)
libname ?= libtest
importlib_flags = -ldl -lboost_filesystem
parser: $(obj)
g++ -o $# $^
%.o: src/%.cpp
ifeq ($<,src/$(libname).cpp)
g++ -fpic -c $(libname).cpp -o $(libname).o
g++ -shared -Wl,-soname,$(libname).so.1 -o $(libname).so.1.0.1 $(libname).o -lc
else
g++ -c $< -o $# $(if $(findstring importlib, $<), $(importlib_flags))
endif
.PHONY: clean
clean:
rm -rf *.o *.so* parser
After I run make, I get this:
g++ -c src/libtest.cpp -o libtest.o
g++ -c src/importlib.cpp -o importlib.o -ldl -lboost_filesystem
g++ -c src/token.cpp -o token.o
g++ -c src/main.cpp -o main.o
g++ -o parser libtest.o importlib.o token.o main.o
First line implies makefile goes to else branch, but it should go to ifeq because $< expands to src/libtest.cpp which is equal to src/$(libname).cpp after being expanded. I don't set libname via command line. Why doesn't it work?
IIRC the expansion happens before the rule is actually run, therefore the $< is probably expanded to empty. I.e. the makefile parses the if/else before it runs the rule.
Then when the rule is run, it has "pre-selected" the else part since when it did the decision $< was not what it is during the rule.
So what you can do is use shell script (I am assuming bash), somthing like:
%.o: src/%.cpp
if [[ "$<" == "src/$(libname).cpp" ]] ; then \
g++ -fpic -c $(libname).cpp -o $(libname).o ; \
g++ -shared -Wl,-soname,$(libname).so.1 -o $(libname).so.1.0.1 $(libname).o -lc ; \
else \
g++ -c $< -o $# $(if $(findstring importlib, $<), $(importlib_flags)) ; \
fi
Note bash/shell vars are written like $${shell_var} and makefile vars are $(make_var) - just incase you need them!
Also note if you want to specifically use BASH add this to the top of your makefile:
SHELL:=/bin/bash
Related
I am trying to set an if test for a specific file in my Makefile to compile it with different flags:
.f90.o:
ifeq ($<,main.f90)
#echo ok $<
$(F90) -c $< -o $#
else
#echo nope $<
$(F90) $(F90FLAGS) $(DEBUG) $(INCL) -c $< -o $#
endif
..and despite my efforts I am getting only:
nope main.f90
mpif90 -O2 -g -fbacktrace -fPIC -c main.f90 -o main.o
The ifeq conditional you have used is processed by Make at parse time, not when the recipe is executed. The macro $< is empty when your script is parsed so your recipe only ever contains the latter two lines.
One solution is to provide two recipes, one for your special case and then a pattern recipe for the rest:
main.o:main.f90
$(F90) -c $< -o $#
.f90.o:
$(F90) $(F90FLAGS) $(DEBUG) $(INCL) -c $< -o $#
Is there a way to get the prerequisite corresponding to a target in the Makefile (GNU Make)?
For instance, consider the following Makefile:
CXX = g++
CFLAGS = -Wall
MODULE_NAME = myRenderer
BUILD_DIR = bin
SOURCE_FILES = renderer/tracer.cpp renderer/lights/DiffuseLight.cpp renderer/materials/ScatterUtils.cpp
OBJECT_FILES = $(patsubst %,$(BUILD_DIR)/%, $(notdir $(SOURCE_FILES:.cpp=.o)))
$(BUILD_DIR)/$(MODULE_NAME): $(OBJECT_FILES)
$(CXX) -o $# $^
$(OBJECT_FILES): $(SOURCE_FILES)
#mkdir -p "$(BUILD_DIR)"
$(CXX) $(CFLAGS) -I. -c $< -o $#
when I run make, I can see that the following commands get executed:
g++ -Wall -I. -c renderer/tracer.cpp -o bin/tracer.o
g++ -Wall -I. -c renderer/tracer.cpp -o bin/DiffuseLight.o
g++ -Wall -I. -c renderer/tracer.cpp -o bin/ScatterUtils.o
g++ -o bin/myRenderer bin/tracer.o bin/DiffuseLight.o bin/ScatterUtils.o
And obviously, this fails to build the executable as it's using only the first prerequisite i.e. renderer/tracer.cpp to generate all the object files because I am using the $< automatic variable in the recipe command for the $(OBJECT_FILES) target.
I wish to know how to fix my Makefile to be able to execute these commands:
g++ -Wall -I. -c renderer/tracer.cpp -o bin/tracer.o
g++ -Wall -I. -c renderer/lights/DiffuseLight.cpp -o bin/DiffuseLight.o
g++ -Wall -I. -c renderer/materials/ScatterUtils.cpp -o bin/ScatterUtils.o
g++ -o bin/myRenderer bin/tracer.o bin/DiffuseLight.o bin/ScatterUtils.o
I cannot seem to find the right automatic variable or a way to fetch the right source file to build a given object file.
As suggested by Matt you have (at least) two options:
A compilation rule:
# $(1): source file
define MY_RULE
$$(patsubst %.cpp,$$(BUILD_DIR)/%.o,$$(notdir $(1))): $(1)
#mkdir -p "$$(BUILD_DIR)"
$$(CXX) $$(CFLAGS) -I. -c $$< -o $$#
endef
$(foreach f,$(SOURCE_FILES),$(eval $(call MY_RULE,$(f))))
Note the $$ used to escape the first expansion (see The eval Function for a detailed explanation).
The vpath directive:
vpath %.cpp $(dir $(SOURCE_FILES))
$(BUILD_DIR)/%.o: %.cpp
#mkdir -p "$(BUILD_DIR)"
$(CXX) $(CFLAGS) -I. -c $< -o $#
I'm doing a Makefile to make objects with the same gcc command. This file looks like this:
SRCLIB = main.c srv.c
OBJLIB = main.o srv.o
CC = gcc
CCFLAGS = -Wall -Werror
$(OBJLIB) : $(SRCLIB)
$(CC) $(CCFLAGS) -c $^ -o $#
The objetive is to execute this like:
gcc -Wall -c read_line.c -o read_line.o
gcc -Wall -c client.c -o client.o
But I don't know how to do it, and everything I tested is not working. Is it even possible to do this in a Makefile?
Your makefile expands to this, after the variables are expanded:
main.o srv.o : main.c srv.c
$(CC) $(CCFLAGS) -c $^ -o $#
In make, using multiple targets in explicit rules like this is the same as writing the rule multiple times, once for each target. So, this is the same as this:
main.o : main.c srv.c
$(CC) $(CCFLAGS) -c $^ -o $#
srv.o : main.c srv.c
$(CC) $(CCFLAGS) -c $^ -o $#
This means that if either of the source files changes, BOTH object files will be recreated (since each object depends on both sources, not just their own source file).
Further, in your compile line you use the variable $^ which expands to all the prerequisites. So your compile lines will expand to:
gcc -Wall -Werror -c main.c srv.c -o main.o
gcc -Wall -Werror -c main.c srv.c -o srv.o
which is illegal: if you use -c with the -o option you can only compile one source file.
Make has built-in rules that already know how to compile files, so there's no need to write your own. You can just write this:
SRCLIB = main.c srv.c
OBJLIB = main.o srv.o
CC = gcc
CCFLAGS = -Wall -Werror
.PHONY: all
all: $(OBJLIB)
and that's all you need.
I am trying to build my targets with wildcards. Here is my Makefile:
BINARY = main
LDSCRIPT = stm32f4-discovery.ld
PREFIX ?= arm-none-eabi
CC = $(PREFIX)-gcc
LD = $(PREFIX)-gcc
OBJCOPY = $(PREFIX)-objcopy
CFLAGS += -Os -g \
-Wall -Wextra -Wimplicit-function-declaration \
-Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
-Wundef -Wshadow \
-I$(TOOLCHAIN_DIR)/include \
-fno-common -mcpu=cortex-m4 -mthumb \
-mfloat-abi=hard -mfpu=fpv4-sp-d16 -MD -DSTM32F4
LDSCRIPT ?= $(BINARY).ld
LDFLAGS += --static -lc -lnosys -L$(TOOLCHAIN_DIR)/lib \
-L$(TOOLCHAIN_DIR)/lib/stm32/f4 \
-T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \
-mthumb -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16
OBJS += $(BINARY).o
all: images
images: $(BINARY).images
%.images: %.bin
##printf "*** $* images generated ***\n"
%.bin: %.elf
##printf " OBJCOPY $(*).bin\n"
$(Q)$(OBJCOPY) -Obinary $(*).elf $(*).bin
%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/libopencm3_stm32f4.a
##printf " LD $(subst $(shell pwd)/,,$(#))\n"
$(Q)$(LD) -o $(*).elf $(OBJS) -lopencm3_stm32f4 $(LDFLAGS)
%.o: %.c Makefile
##printf " CC $(subst $(shell pwd)/,,$(#))\n"
$(Q)$(CC) $(CFLAGS) -o $# -c $<
clean:
$(Q)rm -f *.o
$(Q)rm -f *.d
$(Q)rm -f *.elf
$(Q)rm -f *.bin
-include $(OBJS:.o=.d)
When I make, I get the error:
make: *** No rule to make target `main.bin', needed by `main.images'. Stop.
I am trying to make a single image, so I can change each % to $(BINARY), and this works, but I would like to figure out why this isn't working.
You are likely missing a dependency somewhere down the chain.
Note: Some people forget that the "Makefile" itself, when placed on the dependency line - is also checked for existance. Double check that you haven't renamed it.
Like #MadScientist recommends, "make -d" will be your friend here. Use that to locate the rule/file that should have been found but was not.
I simplified your example (on Linux) and got the same type of error with:
Makefile:
all: main.out
%.out: %.elf
g++ $^ -o $#
%.elf: %.obj
mv $^ $#
%.obj: %.cpp Makefile
g++ -c $^ -o $#
Create main.cpp, see it work, then rename main.cpp to something else that it can't find, run again, see it fail.
Now rename the Makefile itself, see the same failure.
I have a gnu makefile template that has served me well, but when I try to specify a compiler other than the first g++ in my path, it fails.
Here's the template.
CXX = g++
CXXFLAGS = $(INC) $(LIB) -Wall
INC = -I./ -I/usr/local/include
LIB = -L/usr/local/lib
SRCS = \
blah1.cpp
blah2.cpp
OBJS = $(SRCS:.cpp=.o)
DEPS = $(SRCS:.cpp=.d)
PROG = myprog
$(PROG): $(OBJS)
$(CXX) $(CXXFLAGS) -o $# $(OBJS)
%.d: %.cpp
#set -e; rm -f $#; \
$(CXX) -MM $(CXXFLAGS) $< > $#.$$$$; \
sed 's,\($*\)\.o[ :]*,\1.o $# : ,g' < $#.$$$$ > $#; \
rm -f $#.$$$$
debug: CXXFLAGS += -O0 -DDEBUG -ggdb
debug: $(PROG)
-include $(DEPS)
.PHONY: clean
clean:
rm -f $(DEPS) $(OBJS) $(PROG)
When I change the compiler from g++ to something like /usr/local/bin/g++46, it still compiles with g++ (/usr/bin/g++ to be exact). Why?
P.S. Any criticisms with the template are welcome. I'm not very comfortable with gnu make; I just crammed and searched the web for a day to come up with this.
You haven't specified your own rule for how to build object files, so Make uses the default implicit rule, which is:
$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c
Note $(CXX), not $(CC), which specifies the default C compiler.