I Tested a simple "hello world" application for RedPitaya FPGA: RedPitayaHelloWorldVHDL.
It takes a clock from PACKAGE_PIN U18 and U19, devides it by frequency to receive 1Hz, and outputs counter to LEDs. After making a bitstram and writing to FPGA by command:
cat bitstram.bit > /dev/xdevcfg
LEDs blinks good, but Linux on board of RedPitaya hangsup. Why it's happening? and how to avoid it?
You need to instantiate a Zynq "PS7" component in your design, that is the interface between the Linux SoC part and the FPGA fabric, there is also a wizard in Vivado to configure this. If this component is not in the design then programming the bitstream crashes the SoC.
If the Linux on Red Pitaya also assumes the presence of any AXI slaves on the FPGA fabric side, omitting these from the design might also cause a lock up, but this is less likely to be the problem.
Related
I completed Anton Potočniks' introductory guide to the red pitaya board and I am now able to send commands from the linux machine running on the SoC to its FPGA logic.
I would like to further modify the project so that I can control the phase of the signal that is being transmitted via the red pitayas' DAC. Some pins (from 7 down to 1) of the first GPIO port were still unused so I started setting them from within the OS and used the red pitaya's LEDs to confirm that they were being set without interfering with the functionality of Anton Potočnik's "high bandwidth averager".
I then set the DDS_compilers' to Phase Offset Programmability to "streaming" mode so that it can be configured on the fly using the bits that are currently controling the red pitaya's LEDs. I used some slices to connect my signals to the AXI4-Stream Constant IP core, which in turn drives the DDS compiler.
Unfortunately the DAC is just giving me a constant output of 500 mV.
I created a new project with a testbench for the DDS compiler, because synthesis takes a long time and doesn't give me much insight into what is happening.
Unfortunately all the output signals of the DDS compiler are undefined.
My question:
What am I doing wrong and how can I proceed to control DACs' phase?
EDIT1; here is my test bench
The IP core is configured as follows, so many of the control signals that I provided should not be required:
EDIT2; I changed declarations of the form m_axis_data_tready => '0' to m_axis_phase_tready => m_axis_phase_tready_signal. I also took a look at the wrapper file called dds_compiler_0.vhd and saw that it treats both m_axis_phase_tready and m_axis_data_tready as inputs.
My simulation results remained unchanged...
My new test bench can be found here.
EDIT3: Vivado was just giving me the old simulation results - creating a new testbench, deleting the file under <project_name>.sim/sim_1/behav/xsim/simulate.log and restarting vivado solved this problem.
I noticed that the wrapper file (dds_compiler_0.vhd) only has five ports:
aclk (in)
s_axis_phase_tvalid (in)
s_axis_phase_tdata (in)
m_axis_data_tvalid (out)
and m_axis_data_tdata (out)
So I removed all the unnecessary control signals and got a new simulation result, but I am still not recieving any useful output from the dds_compiler:
The corresponding testbench can be found here.
I also don't get any valid output when I include the control signals.
The corresponding testbench can be found here.
Looks like m_axis_data_tready is not connected. No data will come out unless that's asserted.
I want to create a basic project in Vivado that takes a value that i input to a client, which is sent to a server I made (in C), and then the server writes that value to a peripheral in Vivado, and then that data in the peripheral is sent to an output pin that assigns to LED's, making the LED light up.
Basically I want to go from client-->server-->peripheral-->LED lights up
For example, in the client (a GUI) I want to give it a value such as 0011, which is received by the server. Then the server writes that value to the peripheral which will then make, in this case, LED0 & LED1 not light, but LED2 & LED3 will light.
I know how to make an AXI4 peripheral in Vivado, and the client-server (TCP/IP) has been made. My question is what code/design block I would need to then take the data written to the peripheral and assign it to the LED's?
Should I make the peripheral a Master or Slave? Overall confused how should i proceed from here. I am using a Red Pitaya (Xilinx Zynq 7010 SoC) connected by an Ethernet cable to my computer.
Also, I thought of running the program on the Red Pitaya by loading the bitstream on to it (using WinSCP) by running the command
cat FILE_NAME.bit > /dev/xdevcfg
in PuTTY (connected to the Pitaya by IP address), then running the server on the pitaya, and then sending the signal from the client for the server to receive. Is that the correct way of approaching it?
If my logic is off in anyway please let me know
I am somewhat thrown by your statements.
First you say "I know how to make an AXI4 peripheral in Vivado"
Next I read: "Should I make the peripheral a Master or Slave?"
Maybe I am wrong but to me it says you don't really know what you are doing.
Simplest is to:
Instance a zynq system.
Add the IP with the name "AXI GPIO". (Which, by the way, is an AXI slave.)
Run the auto connection.
Assign the right I/O pins to the GPIO port. (check your development system manual)
Build the system.
By the way you find the address of the peripheral in the address tab and it normally is 0x0080000000.
You wrote that you made a server (TCP/IP). "All" it has to do is write the received value to a register in the GPIO block. (Here I assume Xilinx has a document which describes how the GPIO block works and has example GPIO drivers.)
I am a newbie here, I used and have my hand on arduino, but now I got task of taking 3000 samples of waveform with 100MSPS with an adc.
As this was impossible with arduino and most of the controller I switch to FPGA,
And bought NUMATO MIMAS v2 (As it has on board 512Mb DDR RAM, which is capable of handling that much fast operation.)
And also bought AD9283 along with it as it has 100MSPS 8bit adc output.
I am using Xilinx ISE, and using Verilog(No specific reason for it).
My PROBLEM is I am unable to interface that inbuilt DDR ram and communicate with it.
Means there are no tutorial to write on that ram and read from it.
So can any one could help me on it?
I think you can read some file from Xilinx about Spartan 6.Like ug416 and ug388 .
Then you can make a Example Design (tutorial) for your board to simulation and communicate with DDR on real board.It is describe in ug416 page 67.You do not code as you creat a MIG IP.It creat a test file automatic.After you simulaion and verify on your board you will familiar with MIG IP.You shoud make sure these questions in this step.Like How many write/read path you will use?How to manage command path?How to addressing?What's the frequency do you need?And so on.
At last you can use MIG by your demand.If you just has only one stream data you will use MIG very easy.Like just use one write path and one read path.
Forgive my English.
I've looked over the info on BSCANE2 in http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf (pg 169 7 Series FPGA Configuration Guide) and I can't quite figure out how to use it based on that descriptions.
I want to be able to use the JTAG port on the KC705 board to shift in some configuration data for our design. I think (based on the description there in the user guide linked above) that the BSCANE2 is what I need to do that... but I really don't understand why all of the pins of the BSCANE2 component seem to have the wrong direction (TDO is an input while all of the other JTAG control sigs like TCK, RESET, TDI are outputs). Initially I had thought that there was an implicit connection from the signals of the JTAG port of the FPGA to the instantiated BSCANE2 component, but that doesn't appear to be the case based on the port directions. I suspect I'm missing some information somewhere and while I have read the docs it's still not clear to me how to actually use the BSCANE2 to do what I'm trying to do.
Any example usage of a BSCANE2 component would be appreciated.
NOTE: the description of the BSCANE2 in the user guide linked above says:
The BSCANE2 primitive allows access between the internal FPGA logic and the JTAG Boundary Scan logic controller. This allows for communication between the internal running design and the dedicated JTAG pins of the FPGA
This sounds exactly like what I need.
Xilinx offers a 8 bit CPU called PicoBlaze that uses a JTAGLoader module to reconfigure the PicoBlaze's instruction ROM at runtime. The JTAGLoader is provided in VHDL for Spartans and Series-7 devices.
But I think JTAG is not a good protocol for data transfer. Especially the JTAG software API is a mess.
What about UART? Most boards have a USB-UART bridge like CP2103 that supports up to 1 MBoud.
I am new to the Zedboard and am working up to transferring a complex hardware accelerator I currently have working on a regular FPGA board. Anyway I want to walk before I can run so have done the Zedboard speedway tutorials and am now toying around with small projects. My first of which being an simple adder accelerator:
-Send 2 numbers to the pl(programmable logic), to reg a and b
-the pl adds the numbers
-an interrupt to the PS(CPU) signals the computation has finished.
-In the ISR the PS reads the result from reg c
For this design I am using 3 registers (a,b,c) in the AXI interconnect, I have created the IP templates using CIP.
Basically though what is the best way send a control signal to enable the addition to the PL. So how should I signal to the PL adder that I have loaded the two numbers in reg a and b and now want to add them?
-Should I create a 1bit signal GPIO interconnect, add a 4th 1 bit control register to the IP? or is there a more 'stylish' way to do this by using the BUS2IPdata signals?
-Or is there another way to create custom PS to PL control enable signals?
Many thanks
Sam
Current idea:
-Build a switch in the user_logic HDL based on the BUS2IPWrCE, so when this is asserted to write to reg B I can then signal an enable signal to my adder? Or will I run into some concurrency issues with the data not being fully written straight away?
So to do this I have created the AXI perph using CIP, then modified the used_logic and two new ports, en and interrupt. Following these instructions I employed these external connections.http://www.programmableplanet.com/author.asp?section_id=2142&doc_id=264841
I then connected these two external connections to GPIO interfaces to provide the required functionality.
In your larger designs, it will be difficult to get performance using a GPIOs to control the scheduling of your accelerators. I suggest setting up FIFOs of command blocks between software and hardware.
For example, your peripheral could implement an AXI Stream slave, to receive commands from software, and an AXI Stream master, to send result indications back to software.
It can assert an interrupt to indicate that there are values in the response FIFO.
For higher performance, set up these FIFOs in DRAM and use AXI read/write masters in your peripheral.