I have a folder witch contains several dynamic library
path/librairie/libfile_1.so
path/librairie/libfile_2.so
I am trying to link those dynamic library to my output program. I tried the following code but it dosent work..
COMPILE: $(OBJ) $(LIB)
$(CC) $(OBJ) -L/path/librairie -l./librairie -o $(OUTPUT_DIR)/$(OUTPUT)
Does somebody can help me ?
Thanks you
I'm not sure what the -l./librairie option is supposed to do. You pass the name of the libraries you want to link with -l, you don't pass a path or directory name.
You want:
$(OUTPUT_DIR)/$(OUTPUT): $(OBJ) $(LIB)
$(CC) $(OBJ) -L/path/librairie -lfile_1 -lfile_2 -o $#
Related
I'm writing a small study project in C. I need to create a dynamic library and configure its use with macros. First, I create object files with the command:
$gcc -fPIC -c ../data_module/data_process.c
$gcc -fPIC -c ../data_libs/data_stat.c
Then I create a dynamic library like this:
$gcc -shared -o data_process.so data_process.o data_stat.o
And finally I build an executable file using this library:
$gcc main_executable_module.o ../data_libs/data_io.o ../yet_another_decision_module/decision.o -L. data_process.so -o test_main
It works and the executable works correctly. But there is a task to configure the library using macros:
Make the necessary changes to the code of the main_executable_module, configuring the use of the dynamic library using macros.
That is, if I understand correctly, you need to add macros to the main_executable_module.o so that you do not use the -L flags during assembly. But I can't find information anywhere on how to do it. Can you please tell me how to implement this or where can I read about it?
UPD: John Bollinger says
It is possible that the word "macros" is intended to be interpreted as makefile macros, which many people instead call (makefile) "variables". That would make this a question about make / makefiles, not about C.
My Makefile:
CC=gcc
LDFLAGS=
CFLAGS=-c -Wall -Wextra -Werror
SOURCES=main_executable_module.c ../data_libs/data_stat.c ../data_libs/data_io.c ../yet_another_decision_module/decision.c ../data_module/data_process.c
DYNLIB=../data_module/data_process.c
STAT=../data_libs/data_stat.c
BUILDDYN=main_executable_module.c ../data_libs/data_io.c ../yet_another_decision_module/decision.c
OBJECTS=$(SOURCES:.c=.o)
OBJBUILDDYN=$(BUILDDYN:.c=.o)
OBJDYNLIB=data_process.o
OBJDATASTAT=data_stat.o
EXECUTABLE=../../build/main
DEXECUTABLE=../../build/Quest_6
DLIBS=data_process.so
all: $(SOURCES) $(EXECUTABLE)
data_stat.a: $(OBJLIB) $(LIBS)
ar -rcs $(LIBS) $(OBJLIB)
data_process.so: $(OBJDYNLIB) $(OBJDATASTAT)
$(CC) -shared -o $(DLIBS) $(OBJDYNLIB) $(OBJDATASTAT)
$(OBJDYNLIB): $(DYNLIB)
$(CC) -fPIC -c $(DYNLIB)
$(OBJDATASTAT): $(STAT)
$(CC) -fPIC -c $(STAT)
build_with_dynamic:$(OBJECTS) $(EXECUTABLE)
$(CC) $(OBJBUILDDYN) -L. $(DLIBS) -o $(DEXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(LDFLAGS) $(OBJECTS) -o $#
.c.o:
$(CC) $(CFLAGS) $< -o $#
clean:
rm -rf $(EXECUTABLE) $(OBJECTS)
lclean:
rm -rf $(LEXECUTABLE) $(OBJECTS) $(LIBS) $(DEXECUTABLE)
rebuild: clean $(SOURCES) $(EXECUTABLE)
The results of the checks revealed nothing. There are two opinions about this task.
Leave everything as above. And in the file itself, add a header process.h. Then everything is assembled and working. And at the same time, if you change the code in the library, rebuild it, and do not rebuild the executable file, then the changes will be taken into account. That is, the idea of a dynamic library is respected.
Implement in such a way that there is no need to include headers in the main_executable_module.c. Then a special library is used for working with dynamic libraries, which allows you to write the path to the library and take individual functions from it. More about it here.
What was meant when it was said about macros, I still did not understand ...
I am creating a Makefile of a Keil based project. I have a working Makefile now, but I have manually written rules for all the source files, something like this:
out/abc.o: ../../../src/modules/abc.c
ARMCC -o $# $(FLAGS) $^
out/def.o: ../../../src/utilities/def.c
ARMCC -o $# $(FLAGS) $^
out/xyz.o: src/xyz.c
ARMCC -o $# $(FLAGS) $^
which has become kinda long. The object files need to be in one directory(/out), but the source files are in different levels and in various folders like utilities, modules etc. Is there a way to shorten my Makefile so that it scans these different levels of source files and creates the object files?
EDIT:
A follow-up question to the answer. My linker rule is something like this, along with the VPATH addition. I added one directory to VPATH and others are still explicitly compiled.
OBJECT_FILES=out/abc.o out/def.o out/xyz.o
out/binary.axf: $(OBJECT_FILES)
ARMLINK $(MANY_FLAGS) $^ -o $#
VPATH=../a/b/c/module
out/%.o : %.c
$(CC) $(C_FLAGS) $(INCLUDE_PATH) -o $# --depend out/%.d $<
I now get an error that there is no rule for abc.o. abc.c which is present in the directory specified in VPATH under module
*** No rule to make target `out/abc.o', needed by `out/binary.axf'. Stop.
You can use VPATH for this. It can search a list of directories for source files. Assuming you can come up with the list of directories:
VPATH = ../../../src src
CC = ARMCC
out/%.o : %.c
$(CC) -o $# $(CFLAGS) -c $<
Can someone explain me how i do a Makefile getting the source files from a folder named src and the header files from a folder named headers? And then the executable files and the object files being stored on the current folder? Just a basic example to help me out ;). thanks
Like this?
OBJ := foo.o bar.o
thing: $(OBJ)
$(CC) $^ -o $#
%.o: src/%.c
$(CC) -c -Iheaders $< -o $#
I want to compile my source files twice with different flags each time. Besides that I need to have these executables which I'll acquire after the compilation in different directories (so I want 'make' to create two folders and put into every folder an executable).
I think that them main problem is that I don't know how to main object files. Think that we can create them with different names (because every set of .o files should somehow differ from the another which has different flags) or put them in the directories where we want to have executables.
Still I have no idea how to do it in elegant way :/
Any help greatly appreciated :)
You haven't given us many details, so I'll suppose you have two source files, foo.c and bar.c, and you're building in two directories, red/ and blue/. Here is a crude makefile that will do the job:
OBJS := foo.o bar.o
RED_OBJS := $(addprefix red/,$(OBJS))
BLUE_OBJS := $(addprefix blue/,$(OBJS))
$(RED_OBJS): red/%.o : %.c
$(CC) -c $< -o $#
$(BLUE_OBJS): blue/%.o : %.c
$(CC) -c $< -o $#
red/red_exec: $(RED_OBJS)
$(CC) $< -o $#
blue/blue_exec: $(BLUE_OBJS)
$(CC) $< -o $#
The following is the Makefile i use. All is well, except for .o should be created in obj/ directory and it's not.
What am i doing wrong please?
After making sure that
src directory contains a.cpp
target directory exists and is empty
obj directory exists and is empty
When make is ran, i see
g++ -pedantic -Wall -c src/a.cpp -o /Users/me/Dropbox/dev/c++/hott/obj/src/a.o
when it should be
g++ -pedantic -Wall -c src/a.cpp -o /Users/me/Dropbox/dev/c++/hott/obj/a.o
What am i doing wrong please?
UPDATE: Nothing seems to change when hardcoding path and not relying on pwd resolution
If you use -o you have to specify the filename, not just the output path. Try:
$(CC) $(FLAGS) $(SOURCES) $(OBJ)/$#
This question may help, too:
What do the makefile symbols $# and $< mean?
Also, you may want to call FLAGS something like CFLAGS, meaning "the flags for compilation".
Edit
Note that you are not using make efficiently, because you are always recompiling all your .o files from your .cpp files. You should instead use a Pattern Rule, so that Make can have rules to only build what is necessary. (ie. "To build any .o file from a .cpp file, do this: ___")
%.o : %.c
$(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $#
You could edit this to include $(OBJ) before the $#.
All is ok when used like this. A small modification from what Jonathon suggested