Can someone explain me how i do a Makefile getting the source files from a folder named src and the header files from a folder named headers? And then the executable files and the object files being stored on the current folder? Just a basic example to help me out ;). thanks
Like this?
OBJ := foo.o bar.o
thing: $(OBJ)
$(CC) $^ -o $#
%.o: src/%.c
$(CC) -c -Iheaders $< -o $#
Related
My makefile always recompiles everything in directory if one header is changed. It's not a problem now but since I'm adding more to my program this is becoming and issue. I don't want to wait for a whole recompile if I add a new variable to a header of a separate class object.
Here is my makefile:
CXX = g++
CPPFLAGS = -I -lm -lsfml-graphics -lsfml-audio -lsfml-window -lsfml-system
OBJ = CR_Main.o CarRental.o CR_Button.o CR_LoginMenu.o CR_TextBox.o CR_UserCreation.o CR_CheckBox.o
DEPS = CarRental.hpp CR_Button.hpp CR_LoginMenu.hpp CR_TextBox.hpp CR_UserCreation.hpp CR_CheckBox.hpp
%.o: %.cpp $(DEPS)
$(CXX) -c -o $# $< $(CPPFLAGS)
CRC.exe: $(OBJ)
$(CXX) -o $# $^ $(CPPFLAGS)
.PHONY: clean
clean:
del *.o *.exe
Thanks in advance!
EDIT:
I was wondering why is it compiling everything in my directory if only 1 out 6 .hpp files are modified on one line? Is something wrong with my makefile or is that how it is?
why is it compiling everything in my directory if only 1 out 6 .hpp files are modified on one line? Is something wrong with my makefile or is that how it is?
"Wrong" might be too strong a word, but yes, the behavior you describe is a consequence of how your makefile is written.
This rule ...
%.o: %.cpp $(DEPS)
$(CXX) -c -o $# $< $(CPPFLAGS)
... says, roughly, that you can build .o files from corresponding .cpp files plus all the files named in variable DEPS. This implies that if that's the rule make selects for building a given .o file, and any of those prerequisites is newer than the target, then the target is out of date and needs to be rebuilt. You have named all your headers in DEPS and you have not provided any other rules for building .o files, so yes, if any of your headers changes, all of the .o files will be rebuilt.
The most simple-minded alternative would be to write a separate rule for each .o, naming the prerequisites of that file only. That is, the corresponding .cpp file and whichever headers it #includes, directly or indirectly.
But you can save yourself a little typing by instead removing the $(DEPS) part from your existing rule, and adding an additional rule for each .o that does not have a recipe but names all the header prerequisites for that file.
Or if, as it appears, you have consistent relationships between source file names and header names, you might do something like this:
CXX = g++
CPPFLAGS = -I.
LIBS = -lsfml-graphics -lsfml-audio -lsfml-window -lsfml-system -lm
MAIN_OBJ = CR_Main.o
MODULE_OBJS = CarRental.o CR_Button.o CR_LoginMenu.o CR_TextBox.o CR_UserCreation.o CR_CheckBox.o
$(MAIN_OBJ): CR_Main.cpp $(MODULE_OBJS:.o=.h)
$(CXX) $(CPPFLAGS) -c -o $# $<
%.o: %.cpp %.h
$(CXX) $(CPPFLAGS) -c -o $# $<
CRC.exe: $(MAIN_OBJ) $(MODULE_OBJS)
$(CXX) -o $# $^ $(LIBS)
# Extra dependencies (guesses for the sake of example):
CarRental.o CR_LoginMenu.o CR_UserCreation.o: CR_TextBox.h CR_CheckBox.h
# No recipe here
.PHONY: clean
clean:
del $(MAIN_OBJ) $(MODULE_OBJS) CRC.exe
Ultimately, though, what you would really like to do is generate all the header dependencies automatically. That makes the project much easier to maintain once you get it initially set up. You can find lots of information about that on the web, some of it in the GNU make manual.
I am creating a Makefile of a Keil based project. I have a working Makefile now, but I have manually written rules for all the source files, something like this:
out/abc.o: ../../../src/modules/abc.c
ARMCC -o $# $(FLAGS) $^
out/def.o: ../../../src/utilities/def.c
ARMCC -o $# $(FLAGS) $^
out/xyz.o: src/xyz.c
ARMCC -o $# $(FLAGS) $^
which has become kinda long. The object files need to be in one directory(/out), but the source files are in different levels and in various folders like utilities, modules etc. Is there a way to shorten my Makefile so that it scans these different levels of source files and creates the object files?
EDIT:
A follow-up question to the answer. My linker rule is something like this, along with the VPATH addition. I added one directory to VPATH and others are still explicitly compiled.
OBJECT_FILES=out/abc.o out/def.o out/xyz.o
out/binary.axf: $(OBJECT_FILES)
ARMLINK $(MANY_FLAGS) $^ -o $#
VPATH=../a/b/c/module
out/%.o : %.c
$(CC) $(C_FLAGS) $(INCLUDE_PATH) -o $# --depend out/%.d $<
I now get an error that there is no rule for abc.o. abc.c which is present in the directory specified in VPATH under module
*** No rule to make target `out/abc.o', needed by `out/binary.axf'. Stop.
You can use VPATH for this. It can search a list of directories for source files. Assuming you can come up with the list of directories:
VPATH = ../../../src src
CC = ARMCC
out/%.o : %.c
$(CC) -o $# $(CFLAGS) -c $<
I have all my source files in a directory called src and I would like all object files to be placed in a directory obj. It is possible to write a generic make rule (that preferably also works with nmake) that will generate the object file corresponding to the source file and place it in the correct directory?
With nmake, you can use an inference rule with paths:
{src\}.c{obj\}.obj:
$(CC) $(CFLAGS) -c -o $# $<
For GNU make you can use pattern rules, like so:
SRCDIR = src
OBJDIR = obj
$(OBJDIR)/%.o : $(SRCDIR)/%.c
$(CC) $(CPPFLAGS) $(CFLAGS) -c -o $# $<
I want to compile my source files twice with different flags each time. Besides that I need to have these executables which I'll acquire after the compilation in different directories (so I want 'make' to create two folders and put into every folder an executable).
I think that them main problem is that I don't know how to main object files. Think that we can create them with different names (because every set of .o files should somehow differ from the another which has different flags) or put them in the directories where we want to have executables.
Still I have no idea how to do it in elegant way :/
Any help greatly appreciated :)
You haven't given us many details, so I'll suppose you have two source files, foo.c and bar.c, and you're building in two directories, red/ and blue/. Here is a crude makefile that will do the job:
OBJS := foo.o bar.o
RED_OBJS := $(addprefix red/,$(OBJS))
BLUE_OBJS := $(addprefix blue/,$(OBJS))
$(RED_OBJS): red/%.o : %.c
$(CC) -c $< -o $#
$(BLUE_OBJS): blue/%.o : %.c
$(CC) -c $< -o $#
red/red_exec: $(RED_OBJS)
$(CC) $< -o $#
blue/blue_exec: $(BLUE_OBJS)
$(CC) $< -o $#
I have makefile that compiles all *.c files in subfolder:
objects := $(patsubst %.c,%.o,$(wildcard *.c))
cobj: $(objects)
$(objects): %.o: %.c
$(CC) -c $< -o $#
I am having trouble trying to do the same from parent folder. Lets say my .c files are in the folder 'csrc'
objects := $(addprefix, csrc/, $(patsubst %.c,%.o,$(wildcard *.c)))
cobj: $(objects)
$(objects): csrc/%.o: %.c
$(CC) -c $< -o $#
i always see "nothing to do for cobj... Any ideas?
Your pattern rule csrc/%.o: %.c translates e.g. csrc/foo.o into foo.c, not csrc/foo.c. Presumably, that is not what you want.
Why not just %.o: %.c?
What Oli Charlesworth said is correct, but there's another mistake. The wildcard function only checks the current directory. As it is now, $(objects) will be empty (I assume there are no source files in the current, parent directory). You will have to specify the path: $(wildcard csrc/*.c)