After Installng Omnetpp 5.5.1 in Ubuntu 18.04 ,For any folder in Omnetpp, make command is not making any sense.
As it showing the following message:
make: Nothing to be done for 'all'.
Even suggested methods on Internet are not working in my case.Please help.
My makefile is following for Aloha Folder.
#
# OMNeT++/OMNEST Makefile for aloha
#
# This file was generated with the command:
# opp_makemake -f --deep
#
# Name of target to be created (-o option)
TARGET = aloha$(D)$(EXE_SUFFIX)
TARGET_DIR = .
# User interface (uncomment one) (-u option)
USERIF_LIBS = $(ALL_ENV_LIBS) # that is, $(TKENV_LIBS) $(QTENV_LIBS) $(CMDENV_LIBS)
#USERIF_LIBS = $(CMDENV_LIBS)
#USERIF_LIBS = $(TKENV_LIBS)
#USERIF_LIBS = $(QTENV_LIBS)
# C++ include paths (with -I)
INCLUDE_PATH =
# Additional object and library files to link with
EXTRA_OBJS =
# Additional libraries (-L, -l options)
LIBS =
# Output directory
PROJECT_OUTPUT_DIR = out
PROJECTRELATIVE_PATH =
O = $(PROJECT_OUTPUT_DIR)/$(CONFIGNAME)/$(PROJECTRELATIVE_PATH)
# Object files for local .cc, .msg and .sm files
OBJS = $O/Host.o $O/Server.o
# Message files
MSGFILES =
# SM files
SMFILES =
#------------------------------------------------------------------------------
# Pull in OMNeT++ configuration (Makefile.inc)
ifneq ("$(OMNETPP_CONFIGFILE)","")
CONFIGFILE = $(OMNETPP_CONFIGFILE)
else
ifneq ("$(OMNETPP_ROOT)","")
CONFIGFILE = $(OMNETPP_ROOT)/Makefile.inc
else
CONFIGFILE = $(shell opp_configfilepath)
endif
endif
ifeq ("$(wildcard $(CONFIGFILE))","")
$(error Config file '$(CONFIGFILE)' does not exist -- add the OMNeT++ bin directory to the path so that opp_configfilepath can be found, or set the OMNETPP_CONFIGFILE variable to point to Makefile.inc)
endif
include $(CONFIGFILE)
# Simulation kernel and user interface libraries
OMNETPP_LIBS = $(OPPMAIN_LIB) $(USERIF_LIBS) $(KERNEL_LIBS) $(SYS_LIBS)
COPTS = $(CFLAGS) $(IMPORT_DEFINES) $(INCLUDE_PATH) -I$(OMNETPP_INCL_DIR)
MSGCOPTS = $(INCLUDE_PATH)
SMCOPTS =
# we want to recompile everything if COPTS changes,
# so we store COPTS into $COPTS_FILE and have object
# files depend on it (except when "make depend" was called)
COPTS_FILE = $O/.last-copts
ifneq ("$(COPTS)","$(shell cat $(COPTS_FILE) 2>/dev/null || echo '')")
$(shell $(MKPATH) "$O" && echo "$(COPTS)" >$(COPTS_FILE))
endif
#------------------------------------------------------------------------------
# User-supplied makefile fragment(s)
# >>>
# <<<
#------------------------------------------------------------------------------
# Main target
all: $(TARGET_DIR)/$(TARGET)
$(TARGET_DIR)/% :: $O/%
#mkdir -p $(TARGET_DIR)
$(Q)$(LN) $< $#
ifeq ($(TOOLCHAIN_NAME),clangc2)
$(Q)-$(LN) $(<:%.dll=%.lib) $(#:%.dll=%.lib)
endif
$O/$(TARGET): $(OBJS) $(wildcard $(EXTRA_OBJS)) Makefile $(CONFIGFILE)
#$(MKPATH) $O
#echo Creating executable: $#
$(Q)$(CXX) $(LDFLAGS) -o $O/$(TARGET) $(OBJS) $(EXTRA_OBJS) $(AS_NEEDED_OFF) $(WHOLE_ARCHIVE_ON) $(LIBS) $(WHOLE_ARCHIVE_OFF) $(OMNETPP_LIBS)
.PHONY: all clean cleanall depend msgheaders smheaders
.SUFFIXES: .cc
$O/%.o: %.cc $(COPTS_FILE) | msgheaders smheaders
#$(MKPATH) $(dir $#)
$(qecho) "$<"
$(Q)$(CXX) -c $(CXXFLAGS) $(COPTS) -o $# $<
%_m.cc %_m.h: %.msg
$(qecho) MSGC: $<
$(Q)$(MSGC) -s _m.cc -MD -MP -MF $O/$(basename $<)_m.h.d $(MSGCOPTS) $?
%_sm.cc %_sm.h: %.sm
$(qecho) SMC: $<
$(Q)$(SMC) -c++ -suffix cc $(SMCOPTS) $?
msgheaders: $(MSGFILES:.msg=_m.h)
smheaders: $(SMFILES:.sm=_sm.h)
clean:
$(qecho) Cleaning $(TARGET)
$(Q)-rm -rf $O
$(Q)-rm -f $(TARGET_DIR)/$(TARGET)
$(Q)-rm -f $(TARGET_DIR)/$(TARGET:%.dll=%.lib)
$(Q)-rm -f $(call opp_rwildcard, . , *_m.cc *_m.h *_sm.cc *_sm.h)
cleanall:
$(Q)$(MAKE) -s clean MODE=release
$(Q)$(MAKE) -s clean MODE=debug
$(Q)-rm -rf $(PROJECT_OUTPUT_DIR)
# include all dependencies
-include $(OBJS:%=%.d) $(MSGFILES:%.msg=$O/%_m.h.d)
This aforementioned file is missing some information like c++ INCLUDE_PATH and EXTRA_OBJS and LIBS.Is this the reason for not being run?Please Help.
The makefile says that 'Nothing to be done' because the executable is present and up to date, so it is indeed nothing to be done. This is not an error.
As you have indicated, you can execute ./aloha and then that throws a runtime error. This is NOT related to the build process.
Related
I am following a code from GitHub (https://github.com/dmalhotra/pvfmm).
There is a Fortran file in ./examples/src/example-f.f90. I have created a subroutine from this example-f.f90 so that I can make an object file out of it and can call this subroutine in our in-house code. The installation guide is given here (https://github.com/dmalhotra/pvfmm/blob/develop/INSTALL).
The Makefile to compile the example-f.f90 is as (https://github.com/dmalhotra/pvfmm/blob/develop/examples/Makefile):
ifndef PVFMM_DIR
PVFMM_DIR=./..
endif
-include $(PVFMM_DIR)/MakeVariables
ifndef CXX_PVFMM
$(error Cannot find file: MakeVariables)
endif
# FC=$(FC_PVFMM) # TODO: for now, FC must be provided by user
# CC=$(CC_PVFMM) # TODO: for now, CC must be provided by user
CXX=$(CXX_PVFMM)
CXXFLAGS=$(CXXFLAGS_PVFMM)
LDLIBS=$(LDLIBS_PVFMM)
RM = rm -f
MKDIRS = mkdir -p
BINDIR = ./bin
SRCDIR = ./src
OBJDIR = ./obj
INCDIR = ./include
TARGET_BIN = \
$(BINDIR)/example1 \
$(BINDIR)/example2 \
$(BINDIR)/example-sctl \
$(BINDIR)/fmm_pts \
$(BINDIR)/fmm_cheb
all : $(TARGET_BIN)
$(BINDIR)/%: $(SRCDIR)/%.f90
-#$(MKDIRS) $(dir $#)
$(PVFMM_DIR)/libtool --mode=link --tag=FC $(FC) $(CXXFLAGS) -I$(INCDIR) $^ $(LDLIBS) -o $#
...
The MakeVariables can be found in the above link.
I changed this make file so that I can make an object file of example-f.f90 (subroutine, I converted as I told before to link it in our in-house code) and also other files in our in-house code and link at the end. The new makefile looks like:
ifndef PVFMM_DIR
PVFMM_DIR=./..
endif
-include $(PVFMM_DIR)/MakeVariables
ifndef CXX_PVFMM
$(error Cannot find file: MakeVariables)
endif
FC_PVMM = mpif90
FC = mpif90
FC=$(FC_PVFMM) # TODO: for now, FC must be provided by user
CC=$(CC_PVFMM) # TODO: for now, CC must be provided by user
CXX=$(CXX_PVFMM)
CXXFLAGS=$(CXXFLAGS_PVFMM)
LDLIBS=$(LDLIBS_PVFMM)
RM = rm -f
MKDIRS = mkdir -p
BINDIR = ./bin
SRCDIR = ./src
OBJDIR = ./obj
INCDIR = ./include
all : $(project_final)
project_final: $(project)
$(PVFMM_DIR)/libtool --mode=link --tag=FC mpif90 $(CXXFLAGS) -I$(INCDIR) $^ $(LDLIBS) -o $#
project: example-f.o
cd ./src && $(MAKE)
example-f.o: $(SRCDIR)/example-f.f90
$(PVFMM_DIR)/libtool --mode=link --tag=FC mpif90 $(CXXFLAGS) -I$(INCDIR) $^ $(LDLIBS) -c $#
...
Kindly note 'project: example-f.o
cd ./src && $(MAKE)' doing to make object files of our inhouse code. In src we have separate makefile to create object files for out in-house code.
But it gives me the following:
cd ./examples && make;
make[1]: Entering directory '/home/bidesh/Coding/FMM/pvfmm-1.3.0/examples'
make[1]: Nothing to be done for 'all'.
make[1]: Leaving directory '/home/bidesh/Coding/FMM/pvfmm-1.3.0/examples'
How can I modify the makefile so that I can compile the whole code that includes example-f.f90 (subroutine) along with other subroutines (in-house code)?
Thanks a lot.
I want to just run make in windows cmd. Goal is just that i can run make in default windows CMD without that i need run make inside MSYSY or CYGWIN.
When i run make command inside windows cmd it shows message:
'uname' is not recognized as an internal or external command,
operable program or batch file.
process_begin: CreateProcess(NULL, uname -m, ...) failed.
####################################################################
# Makefile
#
# OS variable must either be 'posix' or 'win'. E.g. 'make OS=posix'.
# Error is thrown if OS variable is not equal with any of these.
#
####################################################################
.SUFFIXES: # ignore builtin rules
.PHONY: all debug release clean export
####################################################################
# Definitions #
####################################################################
# uniq is a function which removes duplicate elements from a list
uniq = $(strip $(if $1,$(firstword $1) \
$(call uniq,$(filter-out $(firstword $1),$1))))
PROJECTNAME = projectoutput
CONFIG ?= default
SDK_DIR = ../../../..
OBJ_DIR = obj
EXE_DIR = exe
LST_DIR = lst
EXPORT_DIR = export
RTL_DIR = $(SDK_DIR)/util
####################################################################
# Definitions of toolchain. #
# You might need to do changes to match your system setup #
####################################################################
RMDIRS := rm -rf
RMFILES := rm -rf
ALLFILES := /*.*
NULLDEVICE := /dev/null
SHELLNAMES := $(ComSpec)$(COMSPEC)
UNAME := $(shell uname | tr '[:upper:]' '[:lower:]')
DEVICE := x64
ifneq ($(filter arm%, $(shell uname -m)),)
DEVICE := cortexa
endif
ifeq (export,$(findstring export, $(MAKECMDGOALS)))
# Set the default OS for exporting if not specified externally
ifeq (,$(filter $(OS),posix win))
OS:=posix
endif
else
# Try autodetecting the environment: Windows
ifneq ($(SHELLNAMES),)
QUOTE :="
ifeq (,$(filter $(OS),posix win))
OS:=win
endif
ifneq ($(COMSPEC),)
ifeq ($(findstring cygdrive,$(shell set)),)
# We were not on a cygwin platform
NULLDEVICE := NUL
endif
else
# Assume we are making on a Windows platform
# This is a convenient place to override TOOLDIR, DO NOT add trailing
# whitespace chars, they do matter !
SHELL := $(SHELLNAMES)
RMDIRS := rd /s /q
RMFILES := del /s /q
ALLFILES := \*.*
NULLDEVICE := NUL
endif
# Other than Windows
else
ifeq (,$(filter $(OS),posix win))
OS:=posix
endif
endif
endif
# Create directories and do a clean which is compatible with parallell make
$(shell mkdir $(OBJ_DIR)>$(NULLDEVICE) 2>&1)
$(shell mkdir $(EXE_DIR)>$(NULLDEVICE) 2>&1)
$(shell mkdir $(LST_DIR)>$(NULLDEVICE) 2>&1)
ifeq (clean,$(findstring clean, $(MAKECMDGOALS)))
ifneq ($(filter $(MAKECMDGOALS),all debug release),)
$(shell $(RMFILES) $(OBJ_DIR)$(ALLFILES)>$(NULLDEVICE) 2>&1)
$(shell $(RMFILES) $(EXE_DIR)$(ALLFILES)>$(NULLDEVICE) 2>&1)
$(shell $(RMFILES) $(LST_DIR)$(ALLFILES)>$(NULLDEVICE) 2>&1)
endif
endif
ifeq ($(OS),posix)
CC = gcc
LD = ld
AR = ar
else
CC = x86_64-w64-mingw32-gcc
LD = x86_64-w64-mingw32-ld
AR = x86_64-w64-mingw32-ar
endif
####################################################################
# Flags #
####################################################################
INCLUDEPATHS += . \
$(SDK_DIR)/app/common_host/uart \
$(SDK_DIR)/app/common_host/tcp \
$(SDK_DIR)/app/common_host/system \
$(SDK_DIR)/app/common_host/app_assert \
$(SDK_DIR)/app/common_host/app_signal \
$(SDK_DIR)/app/common_host/log \
$(SDK_DIR)/app/common_host/log/config \
INCFLAGS = $(addprefix -I, $(INCLUDEPATHS))
# -MMD : Don't generate dependencies on system header files.
# -MP : Add phony targets, useful when a h-file is removed from a project.
# -MF : Specify a file to write the dependencies to.
DEPFLAGS = \
-MMD \
-MP \
-MF $(#:.o=.d)
# Add -Wa,-ahld=$(LST_DIR)/$(#F:.o=.lst) to CFLAGS to produce assembly list files
override CFLAGS += \
-fno-short-enums \
-Wall \
-c \
-fmessage-length=0 \
-std=c99 \
$(DEPFLAGS)
# Linux platform: if _DEFAULT_SOURCE is defined, the default is to have _POSIX_SOURCE set to one
# and _POSIX_C_SOURCE set to 200809L, as well as enabling miscellaneous functions from BSD and SVID.
# See usr/include/fetures.h for more information.
#
# _BSD_SOURCE (deprecated since glibc 2.20)
# Defining this macro with any value causes header files to expose BSD-derived definitions.
# In glibc versions up to and including 2.18, defining this macro also causes BSD definitions to be
# preferred in some situations where standards conflict, unless one or more of _SVID_SOURCE,
# _POSIX_SOURCE, _POSIX_C_SOURCE, _XOPEN_SOURCE, _XOPEN_SOURCE_EXTENDED, or _GNU_SOURCE is defined,
# in which case BSD definitions are disfavored. Since glibc 2.19, _BSD_SOURCE no longer causes BSD
# definitions to be preferred in case of conflicts. Since glibc 2.20, this macro is deprecated.
# It now has the same effect as defining _DEFAULT_SOURCE, but generates a compile-time warning
# (unless _DEFAULT_SOURCE is also defined). Use _DEFAULT_SOURCE instead.
# To allow code that requires _BSD_SOURCE in glibc 2.19 and earlier and _DEFAULT_SOURCE in glibc
# 2.20 and later to compile without warnings, define both _BSD_SOURCE and _DEFAULT_SOURCE.
#
# OSX platform: _DEFAULT_SOURCE is not used, instead _DARWIN_C_SOURCE is defined by default.
ifeq ($(OS),posix)
override CFLAGS += \
-D_DEFAULT_SOURCE \
-D_BSD_SOURCE
endif
# NOTE: The -Wl,--gc-sections flag may interfere with debugging using gdb.
ifeq ($(OS),posix)
override LDFLAGS += \
-L$(RTL_DIR)/lib/$(UNAME)_$(DEVICE)/gcc/release \
-lstdc++ \
-lpthread \
-lm
else
override LDFLAGS += \
-static \
-lstdc++ \
-lpthread \
-lWs2_32
endif
####################################################################
# Files #
####################################################################
C_SRC += \
$(SDK_DIR)/app/common_host/system/system.c \
$(SDK_DIR)/app/common_host/app_signal/app_signal_$(OS).c \
app.c \
loc.c \
conn.c \
main.c
# this file should be the last added
C_SRC += \
$(SDK_DIR)/app/common/uart/uart_$(OS).c
# Project resources
INC_FILES = $(foreach dir,$(INCLUDEPATHS),$(wildcard $(dir)/*.h))
PROJ_FILES = $(C_SRC) $(INC_FILES) $(RTL_DIR)/lib makefile
DST_DIR = $(EXPORT_DIR)/app/$(PROJECTNAME)/
DST_FILES := $(addprefix $(DST_DIR), $(PROJ_FILES))
####################################################################
# Rules #
####################################################################
C_FILES = $(notdir $(C_SRC) )
#make list of source paths, uniq removes duplicate paths
C_PATHS = $(call uniq, $(dir $(C_SRC) ) )
C_OBJS = $(addprefix $(OBJ_DIR)/, $(C_FILES:.c=.o))
C_DEPS = $(addprefix $(OBJ_DIR)/, $(C_FILES:.c=.d))
OBJS = $(C_OBJS)
vpath %.c $(C_PATHS)
# Default build is debug build
all: debug
debug: CFLAGS += -O0 -g3
debug: $(EXE_DIR)/$(PROJECTNAME)
release: $(EXE_DIR)/$(PROJECTNAME)
# Create objects from C SRC files
$(OBJ_DIR)/%.o: %.c
#echo "Building file: $<"
$(CC) $(CFLAGS) $(INCFLAGS) -c -o $# $<
# Link
$(EXE_DIR)/$(PROJECTNAME): $(OBJS)
#echo "Linking target: $#"
$(CC) $^ $(LDFLAGS) -o $#
clean:
ifeq ($(filter $(MAKECMDGOALS),all debug release),)
$(RMDIRS) $(OBJ_DIR) $(LST_DIR) $(EXE_DIR) $(EXPORT_DIR)
endif
# Collect project files for exporting
$(DST_FILES) : $(addprefix $(DST_DIR), %) : %
#mkdir -p $(dir $#) && cp -pRv $< $#
export: $(DST_FILES)
#echo "Exporting done."
# include auto-generated dependency files (explicit rules)
ifneq (clean,$(findstring clean, $(MAKECMDGOALS)))
-include $(C_DEPS)
endif
Look here:
UNAME := $(shell uname | tr '[:upper:]' '[:lower:]')
You run $(shell uname ...). That starts a shell and runs the command given. If you run make so that it uses cmd.exe as its shell without msys or Cygwin, then it's as if you typed uname | tr '[:upper:]' '[:lower:]' at your cmd.exe prompt, which obviously will fail as you've seen.
If you want to avoid msys or Cygwin then you have to fix ALL of your makefile to not use any POSIX commands, including here.
I have been working with a project that only compiles C sources but I've found I need some assembler too, I'm reticent to inline the asm code in a C file as GCC may not interpret it correctly.
My predecesor created the makefile for the project (apologies, it's fairly long):
# Compiler and options
CC := sparc-rtems-gcc
# The application software binary
TARGET := icu_asw
# Source and build directories
SRCDIR := src
BUILDDIR := obj
TARGETDIR := bin
HDSWROOT := ../../hdsw
BSWTOOLS := ../../bsw/sw/tools
SRCEXT := c
DEPEXT := d
OBJEXT := o
MRAMEXT := img.elf
# Flags, libraries and includes
CFLAGS := -std=gnu99 -Wall -Wextra -g
LIBDRV := $(HDSWROOT)/lib/libdrv.a
INCFLAGS := -I$(HDSWROOT)/include -I$(HDSWROOT)/osal/rtems
# Debug flags
DEBUGFLAGS = -DLOGERROR=1 -DLOGWARN=1 -DLOGDEBUG=1 -DLOGINFO=1 -DMAKECHECKS=1
NODEBUGFLAGS = -DLOGERROR=1 -DLOGWARN=0 -DLOGDEBUG=0 -DLOGINFO=0 -DMAKECHECKS=1
#-----------------------------------------------------------------------
# Build instructions
#-----------------------------------------------------------------------
SOURCES := $(shell find $(SRCDIR) -type f -name *.$(SRCEXT))
OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(SOURCES:.$(SRCEXT)=.$(OBJEXT)))
# Default make
all: $(TARGET)
# Remake
remake: cleaner all
# Clean only objects
clean:
#$(RM) -rf $(BUILDDIR)
# Full clean (objects and binaries)
cleaner: clean
#$(RM) -rf $(TARGETDIR)
# Pull in dependency info for *existing* .o files
-include $(OBJECTS:.$(OBJEXT)=.$(DEPEXT))
# Link (uses an order-only prerequisite for the directories so that they
# don't affect the use of the $^)
$(TARGET): $(OBJECTS) | directories
$(CC) -o $(TARGETDIR)/$(TARGET) $^ $(LIBDRV)
# Make the build and target directories
directories:
#mkdir -p $(TARGETDIR)
#mkdir -p $(BUILDDIR)
# Compile
$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(SRCEXT)
#mkdir -p $(dir $#)
$(CC) $(CFLAGS) $(INCFLAGS) $(NODEBUGFLAGS) -c -o $# $<
#$(CC) $(CFLAGS) $(INCDEP) -MM $(SRCDIR)/$*.$(SRCEXT) > $(BUILDDIR)/$*.$(DEPEXT)
#cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp
#sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT)
#sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT)
#rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp
# Non-File Targets
.PHONY: all remake clean cleaner
I want to also bring in and compile two .S files, so, I edited the following line
SOURCES := $(shell find $(SRCDIR) -type f -name *.$(SRCEXT) -or -name *.$(ASMEXT))
To bring in the .S files, then I edited the OBJECTS to also include the ASM sources ("*.S")
OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(SOURCES:.$(SRCEXT)=.$(OBJEXT)),$(SOURCES:.$(ASMEXT)=.$(OBJEXT)))
But when recompiling with 'make all' I'm getting:
$ make all
make: *** No rule to make target `obj/asi_access.S', needed by `icu_asw'. Stop.
I don't suppose someone could spot where I am going wrong? I think I have not correctly added to the OBJECTS line!
Thanks
The expression $(var:.ext1=.ext2) does not filter by .ext1, i.e.
$(SOURCES:.$(SRCEXT)=.$(OBJEXT)) $(SOURCES:.$(ASMEXT)=.$(OBJEXT))
gives for a test source list the following result
a.o b.o c.S a.c b.c c.o
I.e. you duplicated your files and you have source files in the OBJECTS definition.
The following would be a correct approach:
OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%, \
$(patsubst %.$(SRCEXT),%.$(OBJEXT), \
$(patsubst %.$(ASMEXT),%.$(OBJEXT),$(SOURCES)) \
) \
)
UPDATE: you should consider to use 2 separate object lists, so that you can apply different rules for them, e.g.
SOURCES_C := $(filter %.$(SRCEXT),$(SOURCES))
OBJECTS_C := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(SOURCES_C:%.$(SRCEXT)=%.$(OBJEXT)))
SOURCES_ASM := $(filter %.$(ASMEXT),$(SOURCES))
OBJECTS_ASM := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(SOURCES_ASM:%.$(ASMEXT)=%.$(OBJEXT)))
$(OBJECTS_C): $(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(SRCEXT)
.... C compiler recipe ....
$(OBJECTS_ASM): $(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(ASMEXT)
.... assembler recipe ....
$(TARGET): $(OBJECTS_C) $(OBJECTS_ASM) | directories
I'm trying to get my Makefile to compile only changed source files. In the Makefile below, I would like the targets: %.o : ${SOURCE_DIR}/%.c and %.o : ${SOURCE_DIR}/%.s to only compile if the source file has changed, or the corresponding .o object file does not exist.
Not entirely sure what's wrong here, can someone please offer some advice?
# Project name
# ---------------------------------------------------------------------------------------------------------------------
PROJECT_NAME = stm32f4_template
# Source configuration
# ---------------------------------------------------------------------------------------------------------------------
OUT_DIR = ./Build
SOURCE_DIR = ./Src
SOURCES = main.c
SOURCES += startup.s
C_SOURCES = $(filter %.c, $(SOURCES))
ASM_SOURCES += $(filter %.s, $(SOURCES))
OBJECTS = $(C_SOURCES:.c=.o)
OBJECTS += $(ASM_SOURCES:.s=.o)
# Tools
# ---------------------------------------------------------------------------------------------------------------------
CC = arm-none-eabi-gcc
LD = arm-none-eabi-ld -v
CP = arm-none-eabi-objcopy
OD = arm-none-eabi-objdump
# Compilation, linker and other tool flags
# ---------------------------------------------------------------------------------------------------------------------
CFLAGS = -I./ -c -fno-common -O0 -g -mcpu=cortex-m4 -mthumb
LFLAGS = -nostartfiles -TLinker/memory.ld -TLinker/sections.ld
CPFLAGS = -Obinary
ODFLAGS = -S
# Target: all ---------------------------------------------------------------------------------------------------------
#
all: setup $(PROJECT_NAME).elf
#echo "Done! $?"
# Target: setup -------------------------------------------------------------------------------------------------------
#
setup:
#mkdir -p $(OUT_DIR)
# Target: $(PROJECT_NAME).elf
# ---------------------------------------------------------------------------------------------------------------------
$(PROJECT_NAME).elf: $(OBJECTS)
#echo "Linking $#"
$(LD) $(LFLAGS) -o ${OUT_DIR}/main.elf $(OUT_DIR)/main.o
#echo
# Target %.o (.c sources)
# ---------------------------------------------------------------------------------------------------------------------
%.o : ${SOURCE_DIR}/%.c # --> Execute only if source changed!!!
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $(OUT_DIR)/$#
#echo
# Target %.o (.s sources)
# ---------------------------------------------------------------------------------------------------------------------
%.o : ${SOURCE_DIR}/%.s # --> Execute only if source changed!!!
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $(OUT_DIR)/$#
#echo
# Target: clean
# ---------------------------------------------------------------------------------------------------------------------
clean:
#echo "Cleaning build output..."
#rm -rf $(OUT_DIR)
This rule:
%.o : ${SOURCE_DIR}/%.c # --> Execute only if source changed!!!
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $(OUT_DIR)/$#
The problem is that the target of this rule is main.o, so Make uses it in an attempt to build main.o, because another target demands main.o, but what this rule actually builds is Build/main.o. Make keeps running this rule because it sees that main.o isn't there (and the rule for the elf file uses Build/main.o, which Make keeps rebuilding unawares).
I suggest you change it:
OBJECTS = $(patsubst %.c, $(OUT_DIR)/%.o, $(C_SOURCES))
$(OUT_DIR)/%.o : ${SOURCE_DIR}/%.c # --> this should work
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $#
The same goes for the other %.o rule.
I'm trying to compile an example code where I added a new file under a new directory but I keep getting a dependency problem.
I have added a file "ipc.c" under "/interface".
I have added the source file to "srcs" and also added the directory with "-I/interface".
The Makefile looks as follows:
#
# ======== Makefile ========
#
include ../products.mak
srcs = main_host.c interface/ipc.c
objs = $(addprefix bin/$(PROFILE)/obj/,$(patsubst %.c,%.o$(SUFFIX),$(srcs)))
libs = $(SYSLINK_INSTALL_DIR)/packages/ti/syslink/lib/syslink.a_$(PROFILE)
MAKEVARS = \
SYSLINK_INSTALL_DIR=$(SYSLINK_INSTALL_DIR) \
PKGPATH=$(PKGPATH)
all:
#$(ECHO) "!"
#$(ECHO) "! Making $# ..."
$(MAKE) $(MAKEVARS) PROFILE=debug SUFFIX=v5T togs2_host
$(MAKE) $(MAKEVARS) PROFILE=release SUFFIX=v5T togs2_host
install:
#$(ECHO) "#"
#$(ECHO) "# Making $# ..."
#$(MKDIR) $(INSTALL_DIR)/debug
$(CP) bin/debug/togs2_host $(INSTALL_DIR)/debug
#$(MKDIR) $(INSTALL_DIR)/release
$(CP) bin/release/togs2_host $(INSTALL_DIR)/release
clean::
$(RMDIR) bin
#
#
# ======== rules ========
#
togs2_host: bin/$(PROFILE)/togs2_host
bin/$(PROFILE)/togs2_host: $(objs) $(libs)
#$(ECHO) "##"
#$(ECHO) "## Making $# ..."
$(LD) $(LDFLAGS) -o $# $^ $(LDLIBS)
bin/$(PROFILE)/obj/%.o$(SUFFIX): %.h
bin/$(PROFILE)/obj/%.o$(SUFFIX): %.c
#$(ECHO) "###"
#$(ECHO) "### Making $# ..."
$(CC) $(CPPFLAGS) $(CFLAGS) -o $# $<
# ======== create output directories ========
ifneq (clean,$(MAKECMDGOALS))
ifneq (,$(PROFILE))
ifeq (,$(wildcard bin/$(PROFILE)))
$(shell $(MKDIR) -p bin/$(PROFILE))
endif
ifeq (,$(wildcard bin/$(PROFILE)/obj))
$(shell $(MKDIR) -p bin/$(PROFILE)/obj)
endif
endif
endif
# ======== install validation ========
ifeq (install,$(MAKECMDGOALS))
ifeq (,$(INSTALL_DIR))
$(error must specify INSTALL_DIR)
endif
endif
# ======== toolchain macros ========
ifeq (v5T,$(SUFFIX))
CC = $(CS_ARM_INSTALL_DIR)gcc -c -MD -MF $#.dep -march=armv5t
AR = $(CS_ARM_INSTALL_DIR)ar cr
LD = $(CS_ARM_INSTALL_DIR)gcc
CPPFLAGS = -D_REENTRANT -Dxdc_target_name__=GCArmv5T \
-Dxdc_target_types__=gnu/targets/arm/std.h
CFLAGS = -Wall -ffloat-store -fPIC -Wunused -Dfar= $(CCPROFILE_$(PROFILE)) \
-I. -I/interface $(addprefix -I,$(subst +, ,$(PKGPATH)))
LDFLAGS = $(LDPROFILE_$(PROFILE)) -Wall -Wl,-Map=$#.map
LDLIBS = -lpthread -lc
CCPROFILE_debug = -ggdb -D DEBUG
CCPROFILE_release = -O3 -D NDEBUG
LDPROFILE_debug = -ggdb
LDPROFILE_release = -O3
endif
I keep getting this error:
fatal error: opening dependency file bin/debug/obj/interface/ipc.ov5T.dep: No such file or directory
This is how the the products.mak looks like:
#
# ======== products.mak ========
#
DEPOT = /opt
BIOS_INSTALL_DIR = $(DEPOT)/bios_6_33_01_25
IPC_INSTALL_DIR = $(DEPOT)/ti/ipc_1_23_05_40
SYSLINK_INSTALL_DIR = $(DEPOT)/syslink_2_10_02_17
TI_C6X_INSTALL_DIR = $(DEPOT)/ti/ccsv5/tools/compiler/c6000
CS_ARM_INSTALL_DIR = $(DEPOT)/CodeSourcery/Sourcery_G++_Lite/bin/arm-none-linux-gnueabi-
XDC_INSTALL_DIR = $(DEPOT)/xdctools_3_23_00_32
PKGPATH := $(SYSLINK_INSTALL_DIR)/packages
PKGPATH := $(PKGPATH)+$(BIOS_INSTALL_DIR)/packages
PKGPATH := $(PKGPATH)+$(IPC_INSTALL_DIR)/packages
PKGPATH := $(PKGPATH)+$(XDC_INSTALL_DIR)/packages
PKGPATH := $(PKGPATH)+$
# Use this goal to print your product variables.
.show-products:
#echo "BIOS_INSTALL_DIR = $(BIOS_INSTALL_DIR)"
#echo "IPC_INSTALL_DIR = $(IPC_INSTALL_DIR)"
#echo "SYSLINK_INSTALL_DIR = $(SYSLINK_INSTALL_DIR)"
#echo "TI_ARM_INSTALL_DIR = $(TI_ARM_INSTALL_DIR)"
#echo "TI_C6X_INSTALL_DIR = $(TI_C6X_INSTALL_DIR)"
#echo "CS_ARM_INSTALL_DIR = $(CS_ARM_INSTALL_DIR)"
#echo "XDC_INSTALL_DIR = $(XDC_INSTALL_DIR)"
# ======== standard macros ========
ifneq (,$(wildcard $(XDC_INSTALL_DIR)/bin/echo.exe))
# use these on Windows
CP = $(XDC_INSTALL_DIR)/bin/cp
ECHO = $(XDC_INSTALL_DIR)/bin/echo
MKDIR = $(XDC_INSTALL_DIR)/bin/mkdir -p
RM = $(XDC_INSTALL_DIR)/bin/rm -f
RMDIR = $(XDC_INSTALL_DIR)/bin/rm -rf
else
# use these on Linux
CP = cp
ECHO = echo
MKDIR = mkdir -p
RM = rm -f
RMDIR = rm -rf
endif
I'm not understanding the Makefile completely as it's a code example I'm simply expanding.
For the record: The error "fatal error: opening dependency file [...]: No such file or directory" can also be caused by a too long path. Happened to me on Cygwin/Windows with a path that was way over 200 characters (didn't check exactly).
Got it working.
Needed to add a rule to create the output directories.
So I added
ifeq (,$(wildcard bin/$(PROFILE)/obj/interface))
$(shell $(MKDIR) -p bin/$(PROFILE)/obj/interface)
endif
This makefile is pretty convoluted, so a certain amount of guesswork is required, but I think the trouble is that it doesn't know how to find interface/ipc.c. Try adding this line at the bottom and see if helps:
vpath %.c interface
If it doesn't, we can try some other things. (And if it does, I can suggest some ways to simplify the makefile.)