VHDL Adding and two 8 bits registers in Simple 8bit Processor - overflow

Question

I need to create a simple 8-bit processor that will add and subtract two registers. The result of addition and subtraction must be saved in register A. Data in registers A and B should be entered using the D_IN input.
Then I send register A to the D_OUT output.
Unfortunately, when I try to add these two registers together, I get the error "UUUUUUUU"
Thats my vhdl code
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:43:43 05/27/2020
-- Design Name:
-- Module Name: projekt - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity projekt is
Port (
S : in STD_LOGIC_VECTOR(3 downto 0);
D_IN : in STD_LOGIC_VECTOR(7 downto 0);
D_OUT : out STD_LOGIC_VECTOR(7 downto 0);
A_Out : out STD_LOGIC_VECTOR(7 downto 0);
C : out std_logic
);
end projekt;
architecture Behavioral of projekt is
signal tmp: std_logic_vector (8 downto 0);
signal A : std_logic_vector(7 downto 0);
signal B : std_logic_vector(7 downto 0);
begin
process(A,B,S,D_IN) is
begin
case(S) is
when "0000" =>
A <= A+B;
when "0001" =>
A <= A-B;
when "0010" =>
A <= D_IN;
when "0011" =>
B <= D_IN;
when "0100" =>
B <= A;
when "0101" =>
A <= B;
when "0110" =>
D_OUT <= A;
when others =>
end case;
end process;
tmp <= ('0' & A) + ('0' & B);
C <= tmp(8);
end Behavioral;
And thats my testbench
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:58:50 05/27/2020
-- Design Name:
-- Module Name: /home/ise/projekt/projektTB.vhd
-- Project Name: projekt
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: projekt
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY projektTB IS
END projektTB;
ARCHITECTURE behavior OF projektTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT projekt
PORT(
S : IN std_logic_vector(3 downto 0);
D_IN : IN std_logic_vector(7 downto 0);
D_OUT : OUT std_logic_vector(7 downto 0);
A_Out : OUT std_logic_vector(7 downto 0);
C : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal B : std_logic_vector(7 downto 0) := (others => '0');
signal S : std_logic_vector(3 downto 0) := (others => '0');
signal D_IN : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal A_Out : std_logic_vector(7 downto 0);
signal D_OUT : std_logic_vector(7 downto 0) := (others => '0');
signal C : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: projekt PORT MAP (
S => S,
D_IN => D_IN,
D_OUT => D_OUT,
A_Out => A_Out,
C => C
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
D_IN <= "00000001";
S <= "0010";
wait for 100 ns;
D_IN <= "00000001";
S <= "0011";
wait for 100 ns;
S <= "0000";
wait for 100 ns;
S <= "0110";
-- insert stimulus here
wait;
end process;
END;
When im doing that (result of adding A+B in D_Out, not in A) everything is good. But i need this in A .
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:43:43 05/27/2020
-- Design Name:
-- Module Name: projekt - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity projekt is
Port (
S : in STD_LOGIC_VECTOR(3 downto 0);
D_IN : in STD_LOGIC_VECTOR(7 downto 0);
D_OUT : out STD_LOGIC_VECTOR(7 downto 0);
C : out std_logic
);
end projekt;
architecture Behavioral of projekt is
signal tmp: std_logic_vector (8 downto 0);
signal A : std_logic_vector(7 downto 0);
signal B : std_logic_vector(7 downto 0);
signal test : std_logic_vector (7 downto 0);
signal tmpA : integer;
signal tmpB : integer;
signal tmpSum : integer;
begin
process(A,B,S,D_IN,tmpA,tmpB,tmpSum) is
begin
case(S) is
when "0000" =>
D_OUT <= A+B;
when "0001" =>
D_OUT <= A-B;
when "0010" =>
A <= D_IN;
when "0011" =>
B <= D_IN;
when "0100" =>
B <= A;
when "0101" =>
A <= B;
when "0110" =>
D_OUT <= A;
when others =>
end case;
end process;
tmp <= ('0' & A) + ('0' & B);
C <= tmp(8);
end Behavioral;