I've heard that a in-between page table contains the address of the other page table. But, I've seen it contains less number of bits than those actually required to address the main memory. But, these number of bits are less than the bits required to address physical address space. So, does that mean, some bits are padded with 0s ? So would that imply every page will start at some xxxx(some number of 0s) ?
Since pages have a minimum size and alignment the lower bits of a pointer to a page will always be zero and do not need to be stored.
For example, with a page size of 4096 (0x1000) bytes, addresses to these pages will be always be a multiple of 4096 bytes (e.g. 0x1000, 0x2000, 0x728373000). Notice that the bottom 12 bits are always zero!
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I have been given a page table for a system with 12-bit virtual ad physical addresses and 256-byte pages.
Say I am given an virtual address (in hexadecimal) that reads 0x3E5.
Am I reading this correctly by saying the first hexadecimal, in this case 3, is the page number and the other 2 hexadecimals are the offset?
This because the page sizes, 256-bytes, which is 2^8, meaning 8 bits are for the page size.
Yes, but only if it is a system with byte addressing. Otherwise, you would divide the page size (256 bytes) by the word size to determine the number of addresses within a page, log2 of which would give you the number of page offset bits.
I'm studying operating systems and I have a question about page tables.
I came across this question where it asks how the page table size and entry size changes when the size of the page changes. Say the size of a page is reduced from 8KB to 4KB. Now, my guess is that the size of the page table will be doubled, because now the paging system needs twice as more entries to map the pages to frames.
But for the size of the page table entry, I am not so sure. My guess is that the page table entry will be smaller because the physical address it contains is shorter. This is because the physical address is determined by the page/frame size, and if the page size is smaller, the length of the physical address will be 2^-1 shorter as well.
But is this a good assumption? Is the size of the page table entry determined by the length of the address? Or, is the entry size fixed, regardless of the size of each frame/page? I can't seem to find resources / questions specifically regarding the entries.
Thank you!
I'll try to answer to your example, i.e., reducing the page size from 8KB to 4KB. In that case, as you said, the total number of PTEs (page table entries) is indeed doubled, because the number of pages in the virtual address space is doubled.
For the PTE size: the PTE contains several fields, the most important of them is obviously the frame number, which points to the physical address in which the corresponding page lies. Smaller pages also means smaller frames and longer frame numbers, because the number of bits required to represent a frame number is $log2(physical address space size / frame size)$.
So does it mean that we would have larger PTEs? Not necessarily.
As many other architectural structures, the PTE size is rounded up to the nearest power-of-two. On x86-64 CPUs, e.g., the PTE size is 64 bits, but only 48--52 of them are actually in use. So adding a few bits (only one in your example) to the frame number field would probably leave the PTE size unchanged.
Edit: you can see the PTE structure in the x86-64 architecture here:
https://qph.ec.quoracdn.net/main-qimg-0bcd46d62af1b35820a88f7afc4a50de
(taken from https://www.quora.com/How-is-a-page-walk-implemented )
So Im having trouble understanding some parts to direct mapped caching. I have a byte addressed memory system that has 64KB memory with a 2KB direct-mapped cache. Cache blocks are 32 bytes.
From what I understand and please correct me if i'm wrong, I have 2048B/32B = 64 cache blocks. I need to figure out how many total bits are needed for each cache entry (tag, "dirty" bit, etc).
I believe i'll need 6 index bits (2^6 = 64 (# of blocks))
and 5 offset bits (2^5 = 32 (size of cache block))
Im just having trouble figuring out the rest that are needed.
The bits of a physical address can be split into 3 groups - the least significant group of bits that determine "offset of byte within cache block" and doesn't need to be stored in the tag, the middle group of bits that determine "index of cache block within the cache" and doesn't need to be stored in the tag, and the most significant group of bits that is used to check if the data in the cache is the data you want which must be stored in the tag.
With 64 KiB of physical address space a physical address would have 16 bits; and if your cache is 2048 bytes then (for "direct mapped") the least significant group of bits and the middle group of bits combined must add up to a total of 11 bits. That means the most significant group of bits (which must be stored in the tag) needs to be 5 bits (because 16 bits - 11 bits = 5 bits).
For other bits; you always need something to indicate if the entry is used or empty; if the cache is "write-back" you need a dirty bit but if the cache is "write-through" you don't; if there are multiple CPUs and cache coherency you need more bits for that (e.g. exclusive/shared); and if there's any kind of error detection or correction you need more bits for that (e.g. a "parity bit"). This means the total tag size is at least 6 bits (but may be more).
This question is mostly just to clarify my understanding.
Say I have a 32-bit Computer, with virtual memory space of 2^32 bytes.
Memory paging is used, each page is 2^8 bytes.
So the memory address sizes are 24 bits. Since (2^32/2^8 = 2^24 bytes).
And the offset would be 8 bits? This I do not quite understand. Since I know that the total address is 32, and 24 is already taken by the pages, so the remainder is the offset of 8.
Lastly for the page size. If each physical memory address is stored in 32 bits (4 bytes), the table size would be 2^26 (2^24 * 2^2). Is this correct?
Page Table size = number of entries*size of entry
In your case, each page is 2^8 bytes, that is - you need 8 bits offset. You got that one right.
This leaves us with 24 bits for Page. 2^24 different pages.
Size of page-table for process X is: 2^24*Entry-Size. which is not provided by you here.
Lets assume it needs 32 bits per entry. Then, 2^24*32 = 2^24*2^5 = 2^29 bits.
I'm reading the "Modern Operating System" book. And I'm confused about the "Page Size".
In the book, the author says,
The incoming 16-bit virtual address is
split into a 4-bit page number and
12-bit offset. With 4 bits for the
page number, we can have 16 pages, and
with 12 bits for the offset, we can
address all 4096 bytes within a
page.
Why 4096 bytes? With 12 bits, we can address 4096 entries within a page, correct. But, one entry is an address (in this case, address size = 16 bits). So I think we can address 4096(entry) * 16(bit) = 4096(entry) * 2(byte) = 8KB, but why the book says that we can address 4096 (bytes) ?
Thanks in advance! :)
This is assuming byte-addressed memory (which almost every machine made in the past 30 years uses), so each address refers to a byte, not an entry or address or any other larger value. To hold a 16-bit value, you'll need two consecutive addresses (two bytes).
More than 30 years ago, there used to be machines which were word addressed, which worked like you surmise. But such machines had a tough time dealing with byte-oriented data (such as ASCII characters), and so have fallen out of favor. Nowadays, things like byte addressability, 8-bit bytes and twos-complement integers are pretty much just assumed.
The 12 bits are an offset within a page. The offset is in bytes, not addresses. 2^12 is 4096.
Because with 12 bit, we can address 2^12=4096 slots. Each slot represents an address which size is 1 byte in byte-addressable memory. Hence the total size is 4096*1=4096 bytes = 4KB.
What you are calculating is the page size, i.e. the size of a page in the page table in the memory. As we use 12 bits for the offset, each frame in the physical memory is 2^12=4096K. However, each page in the page table occupies 2^12 entries x 2 bytes = 8K in the memory.
okay so you have 16 bit virtual address let see what does it mean .It means you have 2**16 =65536 bytes.
4 bit page number that means there are 16 pages as 2^4=16
Now You Name The Pages As page1,page2...page16.
Now We are left with 12bits let us see how many address can 12 bits represent 2**12=4096 bytes
65536 bytes could also be achieved by dividing it into 16 pages containing 4096 bytes each as 4096*16=65536