when I try to do make for the makefile it shows me (makefile error missing separator. stop)
my make file is
PROGS = $(patsubst %.c,%,$(SRCS))
all: $(PROGS)
%: %.c
arm-linux-gnueabihf-gcc --static $< -o $#
clean:
rm -f $(PROGS)
I try to use the following command but I could not solve my problem
cat -e -t -v Makefile
SRCS^I=^I$(wildcard^I*.c)^I$
PROGS^I=^I$(patsubst^I%.c,%,$(SRCS))$
all:^I$(PROGS)^I$
%:^I%.c^I$
arm-linux-gnueabihf-gcc^I--static^I$<^I-o^I$#^I$
clean:^I$
rm^I-f^I$(PROGS)^I$ ```
Crazy. You have TAB characters in all the places you don't need them, and you don't have TAB characters in any of the (two) places you must have them. I don't know how you managed that.
In your makefile above the places you MUST have TAB chars are the recipe lines. In other words, your makefile should look like this from cat -e -t -v Makefile:
SRCS = $(wildcard *.c)$
PROGS = $(patsubst %.c,%,$(SRCS))$
all: $(PROGS)$
%: %.c$
^Iarm-linux-gnueabihf-gcc --static $< -o $#$
clean:$
^Irm -f $(PROGS)$
As for configuring your text editor, there are a ton of text editors out there, even on Ubuntu, and we have no idea which one you are using.
I recommend you use a programmer's editor, which has a special mode that understands makefile syntax.
Related
I have a problem with a makefile that's part of a repository. I already posted this question but don't know how to add some code lines after, so I'm trying it here.There is a problem with the makefile that has the common make rules. When I run make, I get the following error: C:\Mios32/include/makefile/common.mk:143: *** multiple target patterns. Stop.
Here's the code from common.mk file from line 142 to 144:
# rule to create .elf file
$(PROJECT_OUT)/$(PROJECT).elf: $(ALL_OBJS)
#$(CC) $(CFLAGS) $(ALL_OBJS) $(LIBS) $(LDFLAGS) -o$#
I'm guessing it's a problem with all_objs, cause these lines right before seem to work:
# rule to create a .hex and .bin file
%.bin : $(PROJECT_OUT)/$(PROJECT).elf
#$(OBJCOPY) $< -O binary $#
%.hex : $(PROJECT_OUT)/$(PROJECT).elf
#$(OBJCOPY) $< -O ihex $#
# rule to create a listing file from .elf
%.lss: $(PROJECT_OUT)/$(PROJECT).elf
#$(OBJDUMP) -w -h -S -C $< > $#
# rule to create a symbol table from .elf
%.sym: $(PROJECT_OUT)/$(PROJECT).elf
#$(NM) -n $< > $#
Here's some additional lines with all_objs:
# list of all objects
ALL_OBJS = $(addprefix $(PROJECT_OUT)/, $(THUMB_OBJS) $(THUMB_CPP_OBJS) $(THUMB_AS_OBJS)
$(ARM_OBJS) $(ARM_CPP_OBJS) $(ARM_AS_OBJS))
# list of all dependency files
ALL_DFILES = $(ALL_OBJS:.o=.d)
And here's some additional lines with Project_out and project:
# where should the output files be located
PROJECT_OUT ?= $(PROJECT)_build
# default linker flags
LDFLAGS += -T $(LD_FILE) -mthumb -u _start -Wl,--gc-section -Xlinker -M -Xlinker -
Map=$(PROJECT_OUT)/$(PROJECT).map -nostartfiles -lstdc++
# default rule
all: dirs cleanhex $(PROJECT).hex $(PROJECT_OUT)/$(PROJECT).bin
$(PROJECT_OUT)/$(PROJECT).lss $(PROJECT_OUT)/$(PROJECT).sym projectinfo
# create the output directories
dirs:
#-if [ ! -e $(PROJECT_OUT) ]; then mkdir $(PROJECT_OUT); fi;
#-$(foreach DIR,$(DIRS), if [ ! -e $(PROJECT_OUT)/$(DIR) ]; \
then mkdir -p $(PROJECT_OUT)/$(DIR); fi; )
I'm pretty new to the whole Make and Makefile topic, so I'm having a hard time figuring out the problem. I appreciate every help.
You should be clear in your question what OS you're working on. It seems from the error message above you're working on Windows. The makefile you're trying to use is very clearly targeted at a UNIX system like GNU/Linux or possibly MacOS.
If you are not familiar with the differences between Windows and UNIX (which are vast and deep) you will definitely have a lot of learning to do before you can even start to get this working.
To use UNIX environments on Windows you need to use something like WSL, or Cygwin, or at least install a MinGW shell environment. When you do that you need to be using UNIX paths, not Windows paths. Windows paths use backslashes (which are escape sequences in UNIX) and drive letters (which have no equivalent in UNIX) and in makefiles in particular the : character is special to make so using paths with drive letters is a problem.
You can debug your makefile by adding $(info ...) functions to show you the value of variables:
# rule to create .elf file
$(info PROJECT_OUT = $(PROJECT_OUT))
$(info PROJECT = $(PROJECT))
$(info ALL_OBJS = $(ALL_OBJS))
$(PROJECT_OUT)/$(PROJECT).elf: $(ALL_OBJS)
#$(CC) $(CFLAGS) $(ALL_OBJS) $(LIBS) $(LDFLAGS) -o$#
With explicit targets I can combine several rules like
foo.o bar.o: $(SOURCES)
cc $< -o $#
This is equivalent of
foo.o: $(SOURCES)
cc $< -o $#
bar.o: $(SOURCES)
cc $< -o $#
But I want to use pattern rules.
I have several troff documents (man, README) and I want to generate .html and .ascii files.
Naive approach is
GROFF := groff
DOCS := man README
DOC_FILES = $(foreach doc,$(DOCS),$(doc).html $(doc).ascii)
CALL_GROFF = $(GROFF) -T$(subst $*.,,$#) -mman $< > $#
%.html %.ascii: %.doc
$(CALL_GROFF)
.DEFAULT: all
all: $(DOC_FILES)
.PHONY: clean
clean:
rm $(DOC_FILES)
But it doesn't work, because make believes that all files are created with one command (much like & in modern make: https://www.gnu.org/software/make/manual/html_node/Multiple-Targets.html)
Obviously I can do
GROFF := groff
DOCS := man README
DOC_FILES = $(foreach doc,$(DOCS),$(doc).html $(doc).ascii)
CALL_GROFF = $(GROFF) -T$(subst $*.,,$#) -mman $< > $#
%.ascii: %.doc
$(CALL_GROFF)
%.html: %.doc
$(CALL_GROFF)
.DEFAULT: all
all: $(DOC_FILES)
.PHONY: clean
clean:
rm $(DOC_FILES)
But it is a kind of copy-paste.
Could it be solved with GNU make?
This is exactly how this works; it's a long-standing feature. From the documentation:
Pattern rules may have more than one target; however, every target must contain a % character. Pattern rules are always treated as grouped targets (see Multiple Targets in a Rule) regardless of whether they use the : or &: separator.
As example states, it was meant to deal with programs that generate more than one output in one invocation, like bison. You can either update your recipe to generate both files in one shot, or keep the rules separated as you do now.
first time here. I am relatively new to makefiles. Here is my current makefile:
# Closure compiler php script path
closure = ../../cli/scripts/Compilers/closure.php
# Destination directory
dest = ../../static/js/
# Build directory
build = build/
# Tell "make" to search build and destination dirs
vpath %.o $(build)
vpath %.js $(dest)
all: main.js
#echo "Done.";
main.js: \
date.o \
jquery.autocomplete.o \
jquery.bullseye.o \
jquery.clickopen.o \
jquery.fbmodal.o \
jquery.helpers.o \
jquery.pulljson.o \
jquery.thumbrotate.o \
jquery.timefmt.o \
jquery.tools.o \
layout.main.o
cat $^ > $(dest)$#
%.o: %.js
php $(closure) $*.js $(build)$#
clean:
rm -rf $(build)*.o
rm -rf $(dest)*.js
The problem is with the following line:
cat $^ > $(dest)$#.
It is supposed to cat all the prerequisite objects (minified javascript) into one final js library. According to makefile docs, $^ is an automatic variable which contains a list of prerequisites with directories they are in. From my experience, it behaves differently depending on wether prerequisite needs to be compiled or not.
If prerequisite is up-to-date, this code works perfectly and $^ contains a list like:
build/date.o build/jquery.autocomplete.o build/jquery.bullseye.o....
However if prerequisite needs a fresh compile, then $^ gets directory part stripped and looks like:
date.o jquery.autocomplete.o jquery.bullseye.o
Only the file which needs a fresh compile gets directory part stripped.
I have managed to work around this issue by replacing
cat $^ > $(dest)$#
with
cat $(addprefix $(build), $(^F) ) > $(dest)$#.
I don't like it because:
It's a hack
$(^F) is semi-deprecated
I want to understand why make behaves like this.
thanks
Look here:
# Tell "make" to search build and destination dirs
vpath %.o $(build)
If Make is looking for foo.o, it will look in the local directory first. If it finds no foo.o there, it will look in $(build) (i.e. build/, and you might reconsider your variable names).
And how would Make build foo.o, if it couldn't find it anywhere? With this rule:
%.o: %.js
php $(closure) $*.js $(build)$#
This rule violates an important guideline of makefiles, in that the target (foo.o) is not the name of the thing actually built (build/foo.o).
Now consider what happens when Make tries to execute this rule:
main.js: date.o ...
cat $^ > $(dest)$#
So if date.o is up to date, it's in build/. Make finds it there, and the automatic variable $^ expands to build/date.o ...
But if date.o must be rebuilt, then Make looks to the %.o rule, which promises to build date.o (not build/date.o), so Make takes that rule at its word and $^ expands to date.o ...
There are several ways to solve this problem. I'd do something like this:
OBJS := date.o jquery.autocomplete.o jquery.bullseye.o ...
OBJS := $(addprefix $(build),$(OBJS))
$(dest)main.js: $(OBJS)
cat $^ > $#
# you might have to tinker with this rule a little
$(build)%.o: %.js
php $(closure) $< $#
I am getting make file error on line 139 below at $(eval $(RULES))
I am really inexperienced in make file syntax.
This is is error it is giving me when I enter make command.
common.mak:139: *** missing separator. Stop.
I tried to removed the tab by single space, \t nothing works.
Do you know what can be the reason?
Thanks
#
# common bits used by all libraries
#
# first so "all" becomes default target
all: all-yes
ifndef SUBDIR
ifndef V
Q = #
ECHO = printf "$(1)\t%s\n" $(2)
BRIEF = CC CXX HOSTCC HOSTLD AS YASM AR LD STRIP CP
SILENT = DEPCC DEPHOSTCC DEPAS DEPYASM RANLIB RM
MSG = $#
M = #$(call ECHO,$(TAG),$#);
$(foreach VAR,$(BRIEF), \
$(eval override $(VAR) = #$$(call ECHO,$(VAR),$$(MSG)); $($(VAR))))
$(foreach VAR,$(SILENT),$(eval override $(VAR) = #$($(VAR))))
$(eval INSTALL = #$(call ECHO,INSTALL,$$(^:$(SRC_DIR)/%=%)); $(INSTALL))
endif
ALLFFLIBS = avcodec avdevice avfilter avformat avresample avutil postproc swscale swresample
# NASM requires -I path terminated with /
IFLAGS := -I. -I$(SRC_PATH)/
CPPFLAGS := $(IFLAGS) $(CPPFLAGS)
CFLAGS += $(ECFLAGS)
CCFLAGS = $(CPPFLAGS) $(CFLAGS)
ASFLAGS := $(CPPFLAGS) $(ASFLAGS)
CXXFLAGS += $(CPPFLAGS) $(CFLAGS)
YASMFLAGS += $(IFLAGS:%=%/) -Pconfig.asm
HOSTCCFLAGS = $(IFLAGS) $(HOSTCPPFLAGS) $(HOSTCFLAGS)
LDFLAGS := $(ALLFFLIBS:%=$(LD_PATH)lib%) $(LDFLAGS)
define COMPILE
$(call $(1)DEP,$(1))
$($(1)) $($(1)FLAGS) $($(1)_DEPFLAGS) $($(1)_C) $($(1)_O) $<
endef
COMPILE_C = $(call COMPILE,CC)
COMPILE_CXX = $(call COMPILE,CXX)
COMPILE_S = $(call COMPILE,AS)
%.o: %.c
$(COMPILE_C)
%.o: %.cpp
$(COMPILE_CXX)
%.s: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) -S -o $# $<
%.o: %.S
$(COMPILE_S)
%.i: %.c
$(CC) $(CCFLAGS) $(CC_E) $<
%.h.c:
$(Q)echo '#include "$*.h"' >$#
%.ver: %.v
$(Q)sed 's/$$MAJOR/$($(basename $(#F))_VERSION_MAJOR)/' $^ > $#
%.c %.h: TAG = GEN
# Dummy rule to stop make trying to rebuild removed or renamed headers
%.h:
#:
# Disable suffix rules. Most of the builtin rules are suffix rules,
# so this saves some time on slow systems.
.SUFFIXES:
# Do not delete intermediate files from chains of implicit rules
$(OBJS):
endif
include $(SRC_PATH)/arch.mak
OBJS += $(OBJS-yes)
FFLIBS := $(FFLIBS-yes) $(FFLIBS)
TESTPROGS += $(TESTPROGS-yes)
LDLIBS = $(FFLIBS:%=%$(BUILDSUF))
FFEXTRALIBS := $(LDLIBS:%=$(LD_LIB)) $(EXTRALIBS)
EXAMPLES := $(EXAMPLES:%=$(SUBDIR)%-example$(EXESUF))
OBJS := $(sort $(OBJS:%=$(SUBDIR)%))
TESTOBJS := $(TESTOBJS:%=$(SUBDIR)%) $(TESTPROGS:%=$(SUBDIR)%-test.o)
TESTPROGS := $(TESTPROGS:%=$(SUBDIR)%-test$(EXESUF))
HOSTOBJS := $(HOSTPROGS:%=$(SUBDIR)%.o)
HOSTPROGS := $(HOSTPROGS:%=$(SUBDIR)%$(HOSTEXESUF))
TOOLS += $(TOOLS-yes)
TOOLOBJS := $(TOOLS:%=tools/%.o)
TOOLS := $(TOOLS:%=tools/%$(EXESUF))
HEADERS += $(HEADERS-yes)
DEP_LIBS := $(foreach NAME,$(FFLIBS),lib$(NAME)/$($(CONFIG_SHARED:yes=S)LIBNAME))
SRC_DIR := $(SRC_PATH)/lib$(NAME)
ALLHEADERS := $(subst $(SRC_DIR)/,$(SUBDIR),$(wildcard $(SRC_DIR)/*.h $(SRC_DIR)/$(ARCH)/*.h))
SKIPHEADERS += $(ARCH_HEADERS:%=$(ARCH)/%) $(SKIPHEADERS-)
SKIPHEADERS := $(SKIPHEADERS:%=$(SUBDIR)%)
HOBJS = $(filter-out $(SKIPHEADERS:.h=.h.o),$(ALLHEADERS:.h=.h.o))
checkheaders: $(HOBJS)
.SECONDARY: $(HOBJS:.o=.c)
alltools: $(TOOLS)
$(HOSTOBJS): %.o: %.c
$(call COMPILE,HOSTCC)
$(HOSTPROGS): %$(HOSTEXESUF): %.o
$(HOSTLD) $(HOSTLDFLAGS) $(HOSTLD_O) $< $(HOSTLIBS)
$(OBJS): | $(sort $(dir $(OBJS)))
$(HOBJS): | $(sort $(dir $(HOBJS)))
$(HOSTOBJS): | $(sort $(dir $(HOSTOBJS)))
$(TESTOBJS): | $(sort $(dir $(TESTOBJS)))
$(TOOLOBJS): | tools
OBJDIRS := $(OBJDIRS) $(dir $(OBJS) $(HOBJS) $(HOSTOBJS) $(TESTOBJS))
CLEANSUFFIXES = *.d *.o *~ *.h.c *.map *.ver *.ho *.gcno *.gcda
DISTCLEANSUFFIXES = *.pc
LIBSUFFIXES = *.a *.lib *.so *.so.* *.dylib *.dll *.def *.dll.a
define RULES
clean::
$(RM) $(OBJS) $(OBJS:.o=.d)
$(RM) $(HOSTPROGS)
$(RM) $(TOOLS)
endef
$(eval $(RULES))
-include $(wildcard $(OBJS:.o=.d) $(HOSTOBJS:.o=.d) $(TESTOBJS:.o=.d) $(HOBJS:.o=.d))
I experienced that same issue when trying to configure ffmpeg for make.
With the current version of ffmpeg's master branch the issue occurs for common.mak at line 160.
To solve this issue I tried the following steps:
git config core.autocrlf false
delete all *.mak files
git reset --hard
These steps alone did not fully solve my problem. Based on the hints regarding the TAB (\t) characters I changed line 160 from
to
Note the arrow (indicating a TAB) at line 160 between $( and eval $(RULES)).
This TAB solved the problem for me. I had to make this change to a further *.mak file. There was the same error message for another file. By the way, Notepad++ is a great tool to insert a TAB as well as for changing the line endings.
Since ffmpeg takes a while for building I decided to share my solution...
I had this exact same issue - when also checking out FFMPEG on Windows but using git.
After running configure and when trying to run make I got the same line:
common.mak:139: *** missing separator. Stop.
As suggested by #MadScientist - Makefiles are particularly fussy not just about tab (\t) but also the choice of line ending (LF vs. CRLF).
This is down to the GNU make command which has to run them - which seems to only respect LF.
So a *nix version, such as this, will work:
And here is the same file under Windows, which won't work:
(Another giveaway is that it is also bigger with double the bytes at the end of each line!)
Bottom line (so to speak) is that you might have to reformat your files - perhaps by using the dos2unix command.
This would still be the case even if not directly cloning from git - but instead downloading a tar/zip that was itself created from a git clone. The end of lines would be preserved.
Or, if using Git (directly as I was) you have to tell it how to handle the end of line characters. When it checks-out/clones and when it commits.
There is a full description of what this means here: http://adaptivepatchwork.com/2012/03/01/mind-the-end-of-your-line/
And how it can be configured (for the old version of git) via the [core].eol setting.
This is also apparent on Windows, when if you run the installer (e.g. http://git-scm.com/downloads) you get a dialogue such as this:
Selecting the final option to "checkout as-is, commit as-is" fixed it for me. Not perhaps the most principled way, but it forced the LF endings to be preserved.
In makefiles, recipe lines MUST start with a TAB character (TAB must be the first character on the line). You cannot have one or more spaces at the beginning of the line, either with or without a following TAB.
I don't know what you mean by: I tried to removed the tab by single space, \t nothing works; that sentence doesn't make sense to me. Hopefully the above paragraph will help you understand what you need to do.
Be sure you're using a text editor (not a word processor) and that your editor doesn't try to "helpfully" change the formatting in your files.
In general, unless you're more experienced with makefiles I don't recommend using the eval function, which requires a pretty clear understanding of the rules make uses for expanding variables and functions to use correctly. I'm not really sure why you're using eval in the context of the RULES variable, anyway; why not just write the rule directly without eval?
How I stop make from saying make: Nothing to be done for 'all'. or make: 'file' is up to date? I'd like my build to be silent when it's not doing anything - there are other places where echo is called to track build progress, so this message is just cluttering things up. I am currently silencing it like this:
all: dependency1 dependency2
#:
Something tells me there must be a better way. Any ideas?
Edit:
I would like to keep command echo working when it does need to build something, however. A good example of what I'm hoping for is along the lines of --no-print-directory, but I can't find any other flags to shut up selected messages.
Maybe make -s?
So after a couple days of reading around the web, it looks like there isn't any better way than what I'm doing. Some people recommended something along the lines of:
all: dependency1 dependency2 | silent
silent:
#:
That is, just depending on the silent target would be enough to quiet things down. Since I didn't come up with any other workable solutions, I'm going with what I have.
You might try...
$ make -q || make
The advantage of doing it this way is that nothing is printed when there is nothing to do but make produces the normal output when it does need to proceed...
To quote (from memory) from the old make(1) man page, BUGS section: There are some things you can't get make to shut up about. Meanwhile, the -s or --silent option may help.
You can set the -s commandline argument to make in the makefile itself, by setting MAKEFLAGS. Nothing is printed unless you explicitely print it, so I use the following makefile to echo invoked commands.
MAKEFLAGS += -s
PROJECT = progname
CC = g++
SDIR = src
ODIR = obj
BDIR = bin
IDIR = include
OBJS = $(patsubst $(SDIR)/%.cc,$(ODIR)/%.o,$(wildcard $(SDIR)/*.cc))
.PHONY: all debug clean
all: $(BDIR)/$(PROJECT)
debug: CFLAGS += -g -Wall -Wextra
debug: all
$(BDIR)/$(PROJECT): $(OBJS)
#mkdir -p $(BDIR)
#echo LINKING $<
#$(CC) -o $# $(OBJS) -I$(IDIR)
$(ODIR)/%.o: $(SDIR)/%.cc
#mkdir -p $(ODIR)
#echo "COMPILING $<"
#$(CC) -o $# -c $< $(CFLAGS)
clean:
#echo "CLEAN"
#rm -rf $(BDIR) $(ODIR)
Removing the MAKEFLAGS variable will print all invoked commands. The Makefile compiles any c++ project where source files (with .cc extension) are put into the src directory and header files are put into the include directory.
make 2>&1 | egrep -v 'Nothing to be done|up to date'