I have an image processing entity that I want to test. I created a package with several stimulus as constant. and I created a driver to apply the stimulus to the DUT.
assuming this is the stimulus package:
package sim_pkg is
type pixel is record
x: std_logic_vector(3 downto 0);
y: std_logic_vector(3 downto 0);
end record;
type array_pixel is array (natural range <>) of pixel;
constant array_1 : array_pixel(0 to 2) :=
(0 => (x"0", x"0"),
1 => (x"1", x"1"),
2 => (x"2", x"2")
);
constant array_2 : array_pixel(0 to 3) :=
(0 => (x"0", x"0"),
1 => (x"1", x"1"),
2 => (x"2", x"2"),
3 => (x"2", x"2")
);
-- more stimulus
...
end package;
and a driver that just applies the requested array to the input of the DUT.
entity img_test is
port(pixel_out : out pixel)
end entity;
architecture foo of img_test is
begin
-- here it supposes to receive a constant name, for example array_1, and apply its element to pixel_out?
end architecture;
I am using Vunit, so I want to send a msg to the driver with the stimulus name. I know how to send a msg but I am having a problem figuring out how to tell the driver which stimuli I want to send.
I know that I can have a procedure to apply the stimulus directly from the testbench but I would like to know if it is possible to have a procedure for example apply_img that takes a stimulus name in my testbench that asks the driver to apply a specific stimulus.
procedure apply_img(start : boolean; some parameter to specify the stimulus);
Is it possible to pass a constant name to another entity in a way that this other entity can use the data object that has this name in vhdl
Pushing and popping the individual elements of the record and creating convenience wrapper subprograms is the recommended way in VUnit but let's explore the options.
What you can do is to store your pixel arrays in an associative array/dictionary type of data structure (https://en.m.wikipedia.org/wiki/Associative_array) where the key is the name you pass to the driver. The driver can then search that data structure for the data associated with the key.
You can create such a data structure from scratch but you can also use the dictionary type shipped with VUnit (https://github.com/VUnit/vunit/blob/master/vunit/vhdl/data_types/src/dict_pkg.vhd). It can only map a string (like your name) to a string so you would have to encode your pixel arrays to string to make that work. What you can do is to store your pixels using the integer vector pointer type (https://github.com/VUnit/vunit/blob/master/vunit/vhdl/data_types/src/integer_vector_ptr_pkg.vhd) and then use its encode/decode functions. Finally I recommend that you write wrapper functions to do everything in one step.
Related
I'm trying to write some fairly generic VHDL code but I'm running into
a situation where I don't understand the standard well enough. (I'm
using VHDL-2008.)
I have written a function that operates on unconstrained
std_logic_vector(s) and returns an unconstrained
std_logic_vector. However, it seems as if I am unable to use this
function as an input to a port in my entity if I pass two
(constrained) std_logic_vectors to it (see instantiation of test_2 in
my example program). However, for some reason it seems to work ok if I
pass bit string literals to it (see instantiation of test_1).
Can someone explain why the I am not allowed to use the concatenate()
function as an input in the instantiation of test_2 while I am allowed
to use a very similar construct in the instantiation of test_1?
To try the code with ModelSim I compiled it with vcom -2008 unconstrained_example.vhd
-- test entity/architecture
library ieee;
use ieee.std_logic_1164.all;
entity test is
port (value : in std_logic_vector);
end entity;
architecture a of test is
begin
-- Intentionally empty
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- Test instantiation
entity testit is
end entity;
architecture a of testit is
signal my_constrained_slv1 : std_logic_vector(5 downto 0);
signal my_constrained_slv2 : std_logic_vector(9 downto 0);
function concatenate(value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector is
begin
return value1 & value2;
end function;
begin
process begin
-- Using the function in this context seems to work ok
report "Value is " & to_string(concatenate(my_constrained_slv1, my_constrained_slv2));
wait;
end process;
-- This instantiation seems to work
test_1: entity work.test
port map (
value => concatenate("000000", "1111111111"));
-- For this entity instantiation I'm getting an error from ModelSim:
-- ** Error: unconstrained_example.vhd(43): (vcom-1383) Implicit signal in port map for port "value" is not fully constrained.
test_2: entity work.test
port map (
value => concatenate(my_constrained_slv1, my_constrained_slv2));
end architecture;
Your function call is not a conversion function and also does not fulfill the requirements to spare an implicit signal declaration.
VHDL-2008 allows such complex expressions in a port association. The language says, that in such cases, an implicit signal will be created:
If the actual part of a given association element for a formal signal port of a block is the reserved word inertial followed by an expression, or is an expression that is not globally static, then the given association element
is equivalent to association of the port with an anonymous signal implicitly declared in the declarative region that immediately encloses the block. The signal has the same subtype as the formal signal port and is the target of an implicit concurrent signal assignment statement of the form:
anonymous <= E;
where E is the expression in the actual part of the given association element. The concurrent signal assignment statement occurs in the same statement part as the block.
Source: IEEE-1076-2017 Draft 5a
signal temp : std_logic_vector; -- derived from the formal in the port association list
temp <= concatenate(my_constrained_slv1, my_constrained_slv2);
test_2: entity work.test
port map (
value => temp
);
end block;
The problem is, that VHDL needs to infer the type for the implicit signal temp from the formal in the port association list (value : std_logic_vector). It knows, that it is a std_logic_vector, but no constraints are known, due to the unconstrained port.
So if port value in entity test is constrained, it should work:
entity test is
port (
value : in std_logic_vector(15 downto 0)
);
end entity;
I came up with the following workaround which is quite ugly but
fulfills my main criteria that I should not have to manually specify
any widths or repeat any information. By hiding away the call to concatenate in a function I can
reuse the function to get the range further down. A short experiment indicates that Vivado 2015.4 accepts this construct as well.
test_2_helper : block
impure function test_2_help_func return std_logic_vector is
begin
-- This is the only place I have to change in case the assignment has to
-- change in some way. (E.g. use other variables or become more complicated, etc.)
return concatenate(my_constrained_slv1, my_constrained_slv2);
end function;
signal test_2_helper_sig : std_logic_vector(test_2_help_func'range);
begin
test_2: entity work.test
port map (
-- It seems to be syntactically legal to use test_2_help_func(test_2_help_func'range)
-- here. Unfortunately this does not work in simulation. Probably because the
-- test_2_help_func does not have any explicit arguments and this may cause issues
-- with the event driven simulation. As a work around the test_2_helper_sig signal
-- is assigned every clock cycle below instead.
value => test_2_helper_sig);
process
begin
-- Note: If you remove the wait for the clock edge and instead use process(all)
-- test_2_helper_sig does not seem to change during simulation, at least in
-- Modelsim 10.6 where I tested this.
wait until rising_edge(clk);
test_2_helper_sig <= test_2_help_func;
end process;
end block;
Note: This is inspired by the following answer: VHDL - Why does using the length attribute directly on a function produce a warning?
I can write:
type bit2_t is array (0 to 1) of bit;
type record0 is record
bit2 : bit2_t;
end record;
But I'd like to do it without defining bit2_t since I don't need it, something like:
type record0 is record
bit2 : array (0 to 1) of bit;
end record;
But if I try that, GHDL 0.34 says:
type mark expected in a subtype indication
You are simply declaring the array instance incorrectly. Instead of
type bit2_t is array (0 to 1) of bit;
type record0 is record
bit2 : array (0 to 1) of bit;
end record;
You need to use
type bit2_t is array (integer range <>) of bit;
type record0 is record
bit2 : bit2_t(0 to 1);
end record;
If you wanted an array of 2-bit arrays of bits, you would use
type bit2_t is array (0 to 1) of bit;
type bit2_array_t is array (integer range <>) of bit2_t;
type record0 is record
bit2 : bit2_array_t(0 to 7); -- '7' or whatever your range needs to be
end record;
You could make this slightly more generic by changing the 7 to a constant, something like bit2 : bit2_array_t(0 to BIT2_ARRAY_LENGTH-1);.
If you want to have a record type that is in some way paramatized, as far as I know you can only achieve this using package generics, as explained in this answer. Your code would use the package as described, and this package would declare your record type with array sizes based on a generic parameter. By instantiating the package with a different value for the generic in each case, your record could have different element sizes for these different cases.
I would note that I do not believe package generics are widely supported by synthesis tools.
Firstly here is what I'm aiming to do, using made-up VHDL syntax...
type type_johns_record is
first_element : std_logic;
second_element: std_logic_vector(3 downto 0);
third_element : boolean;
end record;
....
....
for ii in johns_record'range loop
if johns_record.type_johns_record'val(ii) = .... then
exit;
end if;
end loop;
Hopefully you can see that I'm trying to reference the elements of a record using similar syntax to that which can be used to reference an enumerated type. This however (of course) does not work. Is there a similar syntax that will work? My solution at the moment is to use a record_info field and work using std_logic_vectors as shown below....
type type_johns_record is record
first_element : std_logic;
second_element : std_logic_vector(3 downto 0);
third_element : boolean;
record_info : type_integer_array(2 downto 0);
end record;
function type_johns_record2slv(d : type_johns_record) return std_logic_vector is
begin
return (d.first_element & d.second_element & bool2sl(d.third_element));
end function;
constant johns_record_zero : type_johns_record := (first_element => '0',
second_element => "0000",
third_element => false,
record_info => (1, 4, 1));
-- can be used with any type for which a record_info is known
function get_record_element(input : std_logic_vector; element_number : integer; record_info : type_integer_array) return std_logic_vector is
variable r : type_slv32_array(record_info'length-1 downto 0);
variable pos : integer := 0;
begin
for ii in record_info'range loop
r(ii)(record_info(ii)-1 downto 0) := input(pos+record_info(ii)-1 downto pos);
end loop;
return r(element_number)(record_info(element_number)-1 downto 0);
end function;
I can then use these functions (which are in a package) as follows...
for ii in johns_record.record_info'range loop
if get_record_element(type_johns_record2slv(johns_record), ii, johns_record.record_info) = conv_std_logic_vector(4, johns_record.record_info(ii)) then
exit;
end if;
end loop;
This really sucks and specifying the record_info is error prone and only marginally less time consuming that writing out individual element comparisons line by line. Please offer a better solution!!!
In the IEEE VHDL Standards group, there are actually two proposals relating to this:
http://www.eda.org/twiki/bin/view.cgi/P1076/RecordMemberAttribute
and
http://www.eda.org/twiki/bin/view.cgi/P1076/RecordIntrospection
This does not mean relax, someone else will address the issue. Instead, we need you to comment on it and/or propose additional use models (to help with justification). All of our work is done by volunteers - just like you - no memberships required for basic participation. Much of our work is done on the TWIKI and email reflector and all with VHDL background are welcome to participate. Drop me an email, I will get you setup - see my Stack Exchange profile for details.
To participate, start here: http://www.eda.org/twiki/bin/view.cgi/P1076/
Current proposals:
http://www.eda.org/twiki/bin/view.cgi/P1076/CollectedRequirements
Meeting information:
http://www.eda.org/twiki/bin/view.cgi/P1076/MeetingMinutes
If you'd like to shorten your implementation code slightly, you could write a custom function for each record type (which you already have to do to convert to slv; this would just be a bit longer) that returns the nth element, like:
function get_record_element(input : johns_record_type; element_number : natural) return std_logic_vector is
begin
case element_number is
when 0 =>
return to_slv(input.first_element);
when 1 =>
return to_slv(input.second_element);
...
end function;
...
if get_record_element(johns_record, 2) = ... then
where to_slv is just a set of helper functions to convert other types. Is that more or less tedious than writing a more generic function and using an extra record element?
Instead of a record, then an array may be used, where the index value are based on an enumerated type, and the array elements are a super-set of the required type. Declaration like:
type johns_elements_t is (FIRST, SECOND, THIRD);
subtype johns_type_t is std_logic_vector(3 downto 0); -- Super-set of required types
type johns_array_t is array (johns_elements_t) of johns_type_t;
signal johns_array : johns_array_t;
Use is then like:
for johns_index in johns_array'range loop
if johns_array(johns_index) = "0000" then
exit;
end if;
VHDL attributes can be used to convert the values in the enumerated type between natural, like for example:
for natural_index in 0 to johns_elements_t'pos(johns_elements_t'high) loop
if johns_array(johns_elements_t'val(natural_index)) = "0000" then
Access to elements must then take into account how the contents is used for each elements accessed by the values in the enumerated type, but that is the case anyway when using a record, but now where is no type checking in the compiler. Another use case is:
if johns_array(FIRST)(0) = '1' then -- Used as std_logic
johns_array(FIRST)(0) <= '0';
...
In synthesis, the tool is likely to remove the unused bits in elements where only a subset of the bits are used, so the final design is not larger.
Also, some synthesis tools (for example Altera Quartus II) does not accept functions that return variable length results like std_logic_vector, so a solution for synthesis should taken that into account, since a functions like get_record_element may result in an error.
I am designing a project on Modelsim VHDL where I use two components. Depending on a control input I'll choose which component to use:
If control=0 then the inputs will be ported to the first component.
If control=1 the inputs will be ported to the second component.
However, a compilation error appeared when I wrote "U1: port map..." in an if statement
(can't put an structural statement inside a sequential architecture).
Any ideas how to solve my problem?
There are two possible interpretations to your question:
Situation #1: Your design uses only one of two possible components at a time. The decision of which component to use is done at compile time, i.e., it is written in your code and is impossible to change after the circuit is synthesized.
Situation #2: Your design uses the two components concurrently, and you use a signal to select dynamically one of the possible outputs.
Each situation has a different solution.
Solution for situation #1: Use a generic in your entity, and an if-generate statement in your architecture body. Here is an example:
entity component_selection_at_compile_time is
generic (
-- change this value to choose which component gets instantiated:
COMPONENT_SELECT: in integer range 1 to 2 := 1
);
port (
input: in integer;
output: out integer
);
end;
architecture rtl of component_selection_at_compile_time is
component comp1 is port(input: in integer; output: out integer); end component;
component comp2 is port(input: in integer; output: out integer); end component;
signal comp1_output, comp2_output: integer;
begin
c1: if COMPONENT_SELECT = 1 generate
u1: comp1 port map (input, output);
end generate;
c2: if COMPONENT_SELECT = 2 generate
u2: comp2 port map (input, output);
end generate;
end;
Solution for situation #2: Create a third component. This component will be a wrapper, and will instantiate both of your original components. In certain cases, you can even assign the same inputs to both components. Then use a select signal to chose which output will be forwarded to outside the wrapper.
entity wrapper is
port (
wrapper_input: in integer;
wrapper_output: out integer;
component_select: in integer range 1 to 2
);
end;
architecture rtl of wrapper is
component comp1 is port(input: in integer; output: out integer); end component;
component comp2 is port(input: in integer; output: out integer); end component;
signal comp1_output, comp2_output: integer;
begin
u1: comp1 port map (wrapper_input, comp1_output);
u2: comp2 port map (wrapper_input, comp2_output);
wrapper_output <= comp1_output when component_select = 1 else comp2_output;
end;
The answer to this question depends on the nature of the control input. If the control input is a way of configuring your design at compile time, the desired functionality can be achieved using generics and generate statements. Otherwise....
Based on the way you have worded your question, I am going to assume that this is not the case. I will assume that your design must support both at different times, with the same compiled design. In that case, you must instantiate both components, and route data to both components and somehow indicate to those components when the data is valid and must be processed. For example:
en1 <= not control;
en2 <= control;
U1 : entity work.design1
port map (
data => data,
en => en1
);
U2 : entity work.design2
port map (
data => data,
en => en2
);
In this example, we have created 2 new signals, en1 and en2 which are '1' to enable each of the components at the appropriate time. In each of the instantiated entities, you need to look at the en input to determine when the input data is valid.
Note: Your design may already have a signal similar to en1 or en2. For example, you may have a generic "bus" which has a valid signal, indicating when data on the bus is valid. In that case, you can add something like this, gating the enable signal with bus_valid:
en1 <= not control and bus_valid;
en2 <= control and bus_valid;
I'm developing a description of a BIST engine, and I've been asked by my manager to transition from Verilog to VHDL. I'm very rusty with VHDL, and I can't figure out the right datatype to give to the address register in my code. Most of the time, the address is used to index into arrays.
data : std_logic_vector (2**W-1 downto 0);
...
output = data(addr);
Sometimes though, I need to perform bitwise operations (for example, this code that finds the least-significant 1 in the address):
least_one(0) <= addr(0);
PRIORITY_ENCODER : for i in 1 to (W-1) generate
least_one(i) <= addr(i) and not or_reduce(addr(i-1 downto 0));
end generate PRIORITY_ENCODER;
least_one(W) <= not or_reduce(addr);
Finally, I also rely on the address wrapping around without problem when it overflows (i.e. 1111+1 = 0, and 0-1 = 1111).
So, given all these different uses, what datatype or subtype do I give to the address? When I use integer and the related types, I get errors when I perform the bitwise operations:
ncvhdl_p: *E,APNPFX (filename,17|20): can not make sense of P(...)
When I use std_logic_vector or similiar, I get errors trying to use the address as an array index:
ncvhdl_p: *E,INTYMM (filename,52|17): array index type mismatch [6.4]
I seem to be in a no-win situation here. What data type do I use? Please note, the solution must be synthesizable. Thanks
You want bitwise access and wrapping behaviour:
make addr fundamentally an unsigned vector.
Then you need access to it as an integer:
If you need it as an integer on just one line, use the to_integer call on just that line.
If you need it as an integer in more than one place, create another signal to "shadow" it and put a continuous assignment in the architecture
Like this:
signal addr_int:natural;
....
addr_int <= to_integer(addr);
In this case I would use unsigned type.
This will work very similar to how you are used to std_logic_vector operating in terms of generic bit access, but you can also do arithmetic operations on the address and easily convert to/from integer type, if necessary. Plus it doesn't dirty the sense of std_logic_vector with the "dreaded" std_logic_unsigned package.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
...
architecture myarch of myent is
signal address : unsigned(numbits-1 downto 0);
...
begin
-- as an example
addr_counter : process(sysclk, reset)
begin
if reset = '1' then
address <= (others => '0');
elsif rising_edge(sysclk) then
address <= address + 1;
end if;
end process addr_counter;
...