vhdl structural statement inside a sequential architecture - vhdl

Question

I am designing a project on Modelsim VHDL where I use two components. Depending on a control input I'll choose which component to use:
If control=0 then the inputs will be ported to the first component.
If control=1 the inputs will be ported to the second component.
However, a compilation error appeared when I wrote "U1: port map..." in an if statement
(can't put an structural statement inside a sequential architecture).
Any ideas how to solve my problem?

Answer 1

There are two possible interpretations to your question:
Situation #1: Your design uses only one of two possible components at a time. The decision of which component to use is done at compile time, i.e., it is written in your code and is impossible to change after the circuit is synthesized.
Situation #2: Your design uses the two components concurrently, and you use a signal to select dynamically one of the possible outputs.
Each situation has a different solution.
Solution for situation #1: Use a generic in your entity, and an if-generate statement in your architecture body. Here is an example:
entity component_selection_at_compile_time is
generic (
-- change this value to choose which component gets instantiated:
COMPONENT_SELECT: in integer range 1 to 2 := 1
);
port (
input: in integer;
output: out integer
);
end;
architecture rtl of component_selection_at_compile_time is
component comp1 is port(input: in integer; output: out integer); end component;
component comp2 is port(input: in integer; output: out integer); end component;
signal comp1_output, comp2_output: integer;
begin
c1: if COMPONENT_SELECT = 1 generate
u1: comp1 port map (input, output);
end generate;
c2: if COMPONENT_SELECT = 2 generate
u2: comp2 port map (input, output);
end generate;
end;
Solution for situation #2: Create a third component. This component will be a wrapper, and will instantiate both of your original components. In certain cases, you can even assign the same inputs to both components. Then use a select signal to chose which output will be forwarded to outside the wrapper.
entity wrapper is
port (
wrapper_input: in integer;
wrapper_output: out integer;
component_select: in integer range 1 to 2
);
end;
architecture rtl of wrapper is
component comp1 is port(input: in integer; output: out integer); end component;
component comp2 is port(input: in integer; output: out integer); end component;
signal comp1_output, comp2_output: integer;
begin
u1: comp1 port map (wrapper_input, comp1_output);
u2: comp2 port map (wrapper_input, comp2_output);
wrapper_output <= comp1_output when component_select = 1 else comp2_output;
end;

Answer 2

The answer to this question depends on the nature of the control input. If the control input is a way of configuring your design at compile time, the desired functionality can be achieved using generics and generate statements. Otherwise....
Based on the way you have worded your question, I am going to assume that this is not the case. I will assume that your design must support both at different times, with the same compiled design. In that case, you must instantiate both components, and route data to both components and somehow indicate to those components when the data is valid and must be processed. For example:
en1 <= not control;
en2 <= control;
U1 : entity work.design1
port map (
data => data,
en => en1
);
U2 : entity work.design2
port map (
data => data,
en => en2
);
In this example, we have created 2 new signals, en1 and en2 which are '1' to enable each of the components at the appropriate time. In each of the instantiated entities, you need to look at the en input to determine when the input data is valid.
Note: Your design may already have a signal similar to en1 or en2. For example, you may have a generic "bus" which has a valid signal, indicating when data on the bus is valid. In that case, you can add something like this, gating the enable signal with bus_valid:
en1 <= not control and bus_valid;
en2 <= control and bus_valid;