Suppose I have the following module definition,
module foo(b)
input b;
parameter length = 8;
reg [length-1:0] dummy ;
Now, I want to assign values to this dummy array. For instance I want to make it all 1s. If the length was not parameterized, I could do this,
always #(posedge b)
dummy <= 8'hFF;
But when the length is parameterized, I would hope to do this,
always #(posedge b)
dummy <= length'hFFFF //won't even compile. even if it did, how many F's should there be?
How can I assign ones (or zeroes) to an entire array whose length is parameterized? Or more generally, how can I assign values while specifing the length of a parameterized array?
You can do bit extension:
always # (posedge b)
dummy <= {length{1'b1}};
What is inside the {} is extended by "parameter-1", would be the same as having:
always # (posedge b)
dummy <= {1'b1,1'b1,1'b1,1'b1....};
You can write
always #(posedge b)
dummy <= ~1'b0;
This takes advantage of the fact that Verilog extends operands before applying operators when they are in context-determined expressions.
In SystemVerilog, you can write
always #(posedge b)
dummy <= '1;
Related
What issue occurs in simulation or synthesis if I assign a non-constant value to initial value of for loop variable in VHDL or Verilog?
E.g- If I write a test case like:
module dut(input clk, d, output reg [5:0] q);
integer i, j, k, l;
always #(posedge clk)
begin
for(i =k;j < 4;k++, l++) begin
q[i] <= d;
end
end
endmodule
What will be the issue?
What will be the issue?
The issue is that you can only use the code in simulation. That is: you will not be able to synthesize the code and produce hardware from it.
In synthesis the for-loop is unrolled and hardware is generated for each step through the loop. For that the synthesis tool must know during compile time how often the loop is executed.
A for can be written as a do-while loop
for(<Initialization>;<Condition>;<Iteration>) <Statement>;
<Initialization>;
do
begin
<Statement>;
<Iteration>;
end
while (<Condition>);
So once the clause i=kexecutes, it does not matter what happens to the value of k.
Synthesis requires that the total number of loop iterations be computed at compile time. You have to provide expressions that can be evaluated at compile time. So most likely if the starting and ending iteration values are not constants, the loop will not be synthesizable.
I'm looking into implementing a 4-bit BitSet function at the logic gate level so that it can be written in structural Verilog--I have looked elsewhere for an answer to this question, but can only find C/C++ resources, which operate at a higher level and are mostly unehlpful to me.
The inputs to my interface are a 4-bit number x, a two-bit number index, containing the index to be set or cleared in x, a one-bit number value, containing the value x[index] should be set to (1 or 0 to set or clear, respectively), and a 4-bit output y, which is the final outcome of x.
To my understanding, setting a value in x follows the logic y |= 1 < < x
and clearing a value in x follows y &= 1 < < x, such that if value is equal to 1, sending it through an OR gate with the value already in that index of x will result in a 1, and if value is equal to 0, sending it through an AND gate with the value already in that index of x will result in a 0. This makes sense to me.
It also makes sense that if I am starting with a 4-bit number x, that I might put it through a 1-to-4 DEMUX block (aside from the basic logic gates, I have MUX, DEMUX, magnitude comparators, and binary adders at my disposal) to obtain the individual bits.
What I am unsure about is how to get from the four separate bits to selecting one of them to modify based on the value stored in index using only basic logic gates. Any ideas or pointers for me to start from? Am I thinking about this the right way?
I think you are looking for something like this
reg [3:0] x;
reg [3:0] y;
reg [1:0] index;
// wont work in synthesis
x[index] = 0;
In Verilog you can access each bit individually using [Bit_Number]
But in your case the index is not constant which will end up failing during synthesis. What you can do is write an if else to check the index and change the right index so
if (index == 1) // change bit one
x[1] = 1'b0; // value to assign is zero here
else if(index == 2)
x[2] 1'b0;
A side note:
You can also assign values
// Here x gets the bit 1 and bit 0 of y concatenated with the value of index
x = {y[1:0],index};
So assume
y = 4'b1011;
index = 2'b00;
x = {y[1:0],index} = 1100
I would like to know what is corresponding VHDL code for $clog2(DATA_WIDTH) , for example in this line:
parameter DATA_OUT_WIDTH = $clog2(DATA_WIDTH)
and also for this sign " -: " in this example
if ( Pattern == In[i_count-:PATTERN_WIDTH] )
I will appreciate if anyone can help me.
You can do something like this
constant DATA_OUT_WIDTH : positive := positive(ceil(log2(real(DATA_WIDTH))));
or define a clog2 function encapsulating that expression. ceil and log2 can be found in math_real
use ieee.math_real.all;
In VHDL you can just specify the full range, for example
foo(i_count to i_count + 7)
foo(i_count downto i_count - 7)
Don't use In as an identifier though, it's a reserved word in VHDL.
In addition to Lars example you can easily write a function for finding the ceiling log 2 to determine the number of element address 'bits' necessary for some bus width. Some vendors or verification support libraries provide one already.
The reason there isn't a predefined function in an IEEE library already is expressed in Lars answer, you tend not to use it much, you can assign the value to a constant and an expression can be cobbled together from existing functions.
An example clog2 function
A borrowed and converted log2 routine from IEEE package float_generic:
function clog2 (A : NATURAL) return INTEGER is
variable Y : REAL;
variable N : INTEGER := 0;
begin
if A = 1 or A = 0 then -- trivial rejection and acceptance
return A;
end if;
Y := real(A);
while Y >= 2.0 loop
Y := Y / 2.0;
N := N + 1;
end loop;
if Y > 0.0 then
N := N + 1; -- round up to the nearest log2
end if;
return N;
end function clog2;
The argument A type NATURAL prevents passing negative integer values. Rounding is strict, any remainder below 2.0 causes rounding up.
Note that because this uses REAL and uses division it's only suitable for use during analysis and elaboration. It's a pure function.
You could note Lars example:
constant DATA_OUT_WIDTH : positive := positive(ceil(log2(real(DATA_WIDTH))));
has the same constraints on use for analysis (locally static) and elaboration (globally static). REAL types are generally not supported for synthesis and floating point operations can consume lots of real estate.
The if condition
if ( Pattern == In[i_count-:PATTERN_WIDTH] )
Is a base index (an lsb or msb depending on ascending or descending declared bit order) and a width.
See IEEE Std 1800-2012 (SystemVerilog), 11.5.1 Vector bit-select and part-select addressing.
An indexed part-select is given with the following syntax:
logic [15:0] down_vect;
logic [0:15] up_vect;
down_vect[lsb_base_expr +: width_expr]
up_vect[msb_base_expr +: width_expr]
down_vect[msb_base_expr -: width_expr]
up_vect[lsb_base_expr -: width_expr]
The msb_base_expr and lsb_base_expr shall be integer expressions, and the width_expr shall be a positive constant integer expression. Each of these expressions shall be evaluated in a self-determined context. The lsb_base_expr and msb_base_expr can vary at run time. The first two examples select bits starting at the base and ascending the bit range. The number of bits selected is equal to the width expression. The second two examples select bits starting at the base and descending the bit range.
In VHDL terms this would be a slice with bounds determined from the high index and a width by subtraction.
PATTERN_WIDTH can be globally static (as in a generic constant) as well as locally static (a non-deferred constant). i_count can be variable.
Depending on the declared range of In for example:
constant DATAWIDTH: natural := 8;
signal In_in: std_logic_vector (31 downto 0);
The equivalent expression would be
if Pattern = In_in(i_count downto i_count - DATAWIDTH - 1) then
Note that if the slice length or i_count is less than DATAWIDTH - 1 you'll get a run time error. The - 1 is because In_in'RIGHT = 0.
Without providing the declarations for In (or Pattern) and DATAWIDTH a better answer can't be provided. It really wants to be re-written as VHDL friendly.
Note as Lars indicated in is reserved word (VHDL is not case sensitive here) and the name was changed.
I'm currently working on a design in which I need to do sgn(x)*y, where both x and y are signed vectors. What is the preferred method to implement a synthesizable sgn function in VHDL with signed vectors? I would use the SIGN function in the IEEE.math_real package but it seems like I won't be able to synthesize it.
You don't really need a sign function to accomplish what you need. In numeric_std the leftmost bit is always the sign bit for the signed type. Examine this bit to decide if you need to negate y.
variable z : signed(y'range);
...
if x(x'left) = '1' then -- Negative
z := -y; -- z := -1 * y
else
z := y; -- z := 1 * y
end if;
-- The same as a VHDL-2008 one-liner
z := -y when x(x'left) else y;
Modify as needed if you need to do this with signal assignments.
If you are only interested in using the sign function, the best option is that you define a block in your program whose input is the signed vector x and its output is another bit vector whit the value of the sign.
The way of designing that block is taking the most significative bit of the vector as it indicates the sign. Then, if you write that the output must be one(1(0), others->(0) or how it writes) if that bit is 0 (positive or null value), or every bit are ones(others->(1)) if that bit is 1 (negative value).
You can also define that if input value is 0, the output will also be a 0.
If I have a 32 bit two's complement number and I want to know what is the easiest way to know of two numbers are equal... what would be the fastest bitwise operator to know this? I know xor'ing both numbers and check if the results are zero works well... any other one's?
how about if a number is greater than 0?? I can check the 31'st bit to see if it's greater or equal to 0..but how about bgtz?
Contrary to your comments, '==' is part of Verilog, and unless my memory is a lot worse than usual tonight, it should synthesize just fine. Just for example, you could write something like:
// warning: untested, incomplete and utterly useless in any case.
// It's been a while since I wrote much Verilog, so my syntax is probably a bit off
// anyway (might well be more like VHDL than it should be).
//
module add_when_equal(clock, a, b, x, y, z);
input clock;
input [31:0] a, b, x, y;
output [31:0] z;
reg [31:0] a, b, x, y, z;
always begin: main
#(posedge clock);
if (a == b)
z <= x + y;
end
endmodule;
Verilog also supports the other comparison operators you'd normally expect (!=, <=, etc.). Synthesizers are fairly "smart", so something like x != 0 will normally synthesize to an N-input OR gate instead of a comparator.
// this should work as comparator for Equality
wire [31:0] Cmp1, Cmp2;
wire Equal;
assign Equal = &{Cmp1 ~^ Cmp2}; // using XNOR
assign Equal = ~|{Cmp1 ^ Cmp2}; // using XOR
if you can xor and then compare the result with zero then you can compare a result with some value and if you can compare something to a value then you can just compare the two values without using an xor and a 32 bit zero.